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TNETV2664FIBZWT 数据表(PDF) 67 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 67 Page - Texas Instruments |
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67 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 3 Device Configurations 3.1 System Module Registers The system module includes status and control registers required for configuration of the device. Brief descriptions of the various registers are shown in Table 3-1. System Module registers required for device configurations are discussed in the following sections. Table 3-1. System Module Register Memory Map HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C4 0000 PINMUX0 Pin Multiplexing Control 0 (see Section 3.7.2.1, PINMUX0 Register Description). 0x01C4 0004 PINMUX1 Pin Multiplexing Control 1 (see Section 3.7.2.2, PINMUX1 Register Description). 0x01C4 0008 DSPBOOTADDR DSP Boot Address (see Section 3.4.2.3, DSPBOOTADDR Register). 0x01C4 000C BOOTCOMPLT Boot Complete (see Section 3.4.2.2, BOOTCMPLT Register). 0x01C4 0010 – Reserved 0x01C4 0014 BOOTCFG Device Boot Configuration (see Section 3.4.2.1, BOOTCFG Register). 0x01C4 0018 - 0x01C4 0027 – Reserved 0x01C4 0028 JTAGID JTAG ID (see Section 6.22.1, JTAG ID (JTAGID) Register Description(s)). 0x01C4 002C – Reserved 0x01C4 0030 HPICTL HPI Control (see Section 3.6.2.1, HPI Control Register). 0x01C4 0034 – Reserved 0x01C4 0038 – Reserved 0x01C4 003C MSTPRI0 Bus Master Priority Control 0 (see Section 3.6.1, Switch Central Resource (SCR) Bus Priorities). 0x01C4 0040 MSTPRI1 Bus Master Priority Control 1 (see Section 3.6.1, Switch Central Resource (SCR) Bus Priorities). 0x01C4 0044 – Reserved 0x01C4 0048 VDD3P3V_PWDN VDD 3.3-V I/O Powerdown Control (see Section 3.2, Power Considerations). 0x01C4 004C DDRVTPER DDR2 VTP Enable Register (see Section 6.9.4, DDR2 Memory Controller). 0x01C4 0050 - 0x01C4 0080 – Reserved 0x01C4 0084 TIMERCTL Timer Control (see Section 3.6.2.2, Timer Control Register). 0x01C4 0088 EDMATCCFG EDMA Transfer Controller Default Burst Size Configuration (see Section 3.6.2.3, EDMA TC Configuration Register). 0x01C4 008C – Reserved 3.2 Power Considerations The C6424 provides several means of managing power consumption. As described in the Section 6.3.4, C6424 Power and Clock Domains, the C6424 has one single power domain—the “Always On” power domain. Within this power domain, the C6424 utilizes local clock gating via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the PSC, see Section 6.3.5, Power and Sleep Controller (PSC) and the TMS320C642x Power and Sleep Controller (PSC) User's Guide (literature number SPRUEN8). Some of the C6424 peripherals support additional power saving features. For more details on power saving features supported, see the TMS320C642x DSP Peripherals Overview Reference Guide (literature number SPRUEM3). Copyright © 2007–2009, Texas Instruments Incorporated Device Configurations 67 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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