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TNETV2664FIBZWT 数据表(PDF) 70 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 70 Page - Texas Instruments |
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70 / 249 page  TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com For additional power savings, some of the C6424 peripherals support clock gating within the peripheral boundary. For more details on clock gating and power saving features supported by a specific peripheral, see the TMS320C642x DSP Peripherals Overview Reference Guide (literature number SPRUEM3). 3.3.1.1 Device Clock Frequency The C6424 defaults to PLL bypass mode. To bring the device up to the desired clock frequency, the user should program PLLC1 and PLLC2 after device reset. C6424 supports a FASTBOOT option, where upon exit from device reset the internal bootloader code automatically programs the PLLC1 into PLL mode with a specific PLL multiplier and divider to speed up device boot. While the FASTBOOT option is beneficial for faster boot, the PLL multiplier and divider selected for boot may not be the exact frequency desired for the run-time application. It is the user's responsibility to reconfigure PLLC1 after fastboot to bring the device into the desired clock frequency. Section 3.4.1, Boot Modes, discusses the different fast boot modes in more detail. The user must adhere to the various clock requirements when programming the PLLC1 and PLLC2: • Fixed frequency ratio requirements between CLKDIV1, CLKDIV3, and CLKDIV6 clock domains. For more details on the frequency ratio requirements, see Section 6.3.4, C6424 Power and Clock Domains. • PLL multiplier and frequency ranges. For more details on PLL multiplier and frequency ranges, see Section 6.7.1, PLL1 and PLL2. 3.3.1.2 Module Clock State The clock and reset state for each of the modules is controlled by the Power and Sleep Controller (PSC). Table 3-3 shows the default state of each module after a device-level global reset. The C6424 device has four different module states—Enable, Disable, SyncReset, or SwRstDisable. For more information on the definitions of the module states, the PSC, and PSC programming, see Section 6.3.5, Power and Sleep Controller (PSC) and the TMS320C642x Power and Sleep Controller (PSC) User's Guide (literature number SPRUEN8). Table 3-3. C6424 Default Module States DEFAULT MODULE STATE LPSC # MODULE NAME [PSC Register MDSTATn.STATE] 2 EDMACC SwRstDisable 3 EDMATC0 SwRstDisable 4 EDMATC1 SwRstDisable 5 EDMATC2 SwRstDisable 6 EMAC Memory Controller SwRstDisable 7 MDIO SwRstDisable 8 EMAC SwRstDisable 9 McASP0 SwRstDisable 11 VLYNQ SwRstDisable 12 HPI SwRstDisable 13 DDR2 Memory Controller SwRstDisable SwRstDisable, if configuration pins AEM[2:0] = 000b 14 EMIFA Enable, if configuration pins AEM[2:0] = Others [010b and 101b] 15 PCI SwRstDisable 16 McBSP0 SwRstDisable 17 McBSP1 SwRstDisable 18 I2C SwRstDisable 19 UART0 SwRstDisable 20 UART1 SwRstDisable 70 Device Configurations Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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