TNETV2664FIBZWT datasheet(91/249 Pages) TI1

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TMS320C6424

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SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 3-17. PINMUX0 Register Description (continued)

Bit

Field Name

Description

Pins Controlled

EM_D[15]/GP[36]

EM_D[14]/GP[37]

EM_D[13]/GP[38]

EM_D[12]/GP[39]

EM_D[11]/GP[40]

EM_D[10]/GP[41]

EM_D[9]/GP[42]

EM_D[8]/GP[43]

EM_D[7]/GP[21]

EM_D[6]/GP[20]

EM_D[5]/GP[19]

EM_D[4]/GP[18]

EMIFA Pinout Modes

EM_D[3]/GP[17]

This field does not affect the actual EMIFA operation. It only determines what

EM_D[2]/GP[16]

multiplexed pins in the EMIFA Block serves as EMIFA pins. The pin mux control

EM_D[1]/GP[15]

for some of these pins are controlled by a combination of AEM and PCIEN fields:

EM_D[0]/GP[14]

000b = No EMIFA Mode

EM_R/WGP[35]

None of the multiplexed pins in the EMIFA Block serves as EMIFA pins. They

EM_A[21]/GP[34]

serve as GPIO or PCI pins based on PCIEN setting.

EM_A[20]/PINTA/GP[44]

EM_A[19]/PREQ/GP[45]

001b = Reserved.

EM_A[18]/PRST/GP[46]

EM_A[17]/AD31/GP[47]

010b = EMIFA (Async) Pinout Mode

EM_A[16]/PGNT/GP[48]

Pinout allows up to a maximum of these functions from EMIFA Block: 16-bit

EM_A[15]/AD29/GP[49]

2:0

AEM(1)

EMIFA (Async or NAND) + GPIO + EMAC(RMII). All of the pins listed under the

EM_A[14]/AD27/GP[50]

"Pins Controlled" column serve as EMIFA pins. PINMUX1.PCIEN must be set to

EM_A[13]/AD25/GP[51]

0. PINMUX0.RMII can be set to 0 or 1.

EM_A[12]/PCBE3/GP[89]

EM_A[11]/AD24/GP[90]

011b = Reserved.

EM_A[10]/AD23/GP[91]

100b = Reserved.

EM_A[9]/PIDSEL/GP[92]

EM_A[8]/AD21/GP[93]

101b = 8-bit EMIFA (NAND) Pinout Mode

EM_A[7]/AD22/GP[94]

Pinout allows up to a maximum of these functions from EMIFA Block: 8-bit EMIFA

EM_A[6]/AD20/GP[95]

(NAND) + GPIO + PCI + EMAC(RMII). PINMUX1.PCIEN can be set to 0 or 1.

EM_A[5]/AD19/GP[96]

PINMUX0.RMII can be set to 0 or 1.

EM_A[4]/GP[10]/(PLLMS2)

EM_A[3]/GP[11]

110b through 111b = Reserved.

EM_A[2]/(CLE)/GP[8]/(PLLMS0)

EM_A[1]/(ALE)/GP[9]/(PLLMS1)

EM_A[0]/GP[7]/(AEM2)

EM_CS2/GP[12]

EM_BA[0]/GP[6]/(AEM1)

EM_BA[1]/GP[5]/(AEM0)

The pin mux for these pins are controlled by a

combination of AEM and other fields, including

PCIEN. For the full set of valid configurations of

these pins, see Section 3.7.3.13.2, EMIFA

Block Pin-by-Pin Multiplexing Summary.

(1)

The AEM default value is latched at reset from AEM[2:0] configuration inputs. The latched values are also shown at BOOTCFG.DAEM

(read-only).

Device Configurations

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