TNETV2664FIBZWT datasheet(18/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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2.3

Memory Map Summary

Table 2-5 shows the memory map address ranges of the device. Table 2-6 depicts the expanded map of

the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories

associated with its two processors and various subsystems. To help simplify software development a

unified memory map is used where possible to maintain a consistent view of device resources across all

bus masters.

Table 2-5. Memory Map Summary

START

END

SIZE

C64x+

EDMA PERIPHERAL

PCI

ADDRESS

(Bytes)

MEMORY MAP

0x0000 0000

0x000F FFFF

Reserved

0x0010 0000

0x0010 FFFF

64K

Boot ROM

0x0011 0000

0x007F FFFF

7M-64K

Reserved

0x0080 0000

0x0081 FFFF

128K

L2 RAM/Cache

(1)

0x0082 0000

0x00E0 7FFF

6048K

Reserved

0x00E0 8000

0x00E0 FFFF

32K

L1P RAM/Cache

(1)

Reserved

0x00E1 0000

0x00F0 3FFF

976K

Reserved

0x00F0 4000

0x00F0 FFFF

48K

L1D RAM

0x00F1 0000

0x00F1 7FFF

32K

L1D RAM/Cache

(1)

0x00F1 8000

0x017F FFFF

9120K

Reserved

0x0180 0000

0x01BF FFFF

CFG Space

0x01C0 0000

0x01FF FFFF

CFG Bus Peripherals

0x0200 0000

0x100F FFFF

225M

Reserved

0x1010 0000

0x1010 FFFF

64K

Boot ROM

Reserved

0x1011 0000

0x107F FFFF

7M-48K

Reserved

0x1080 0000

0x1081 FFFF

128K

L2 RAM/Cache

(1)

L2 RAM/Cache

(1)

L2 RAM/Cache

(1)

0x1082 0000

0x10E0 7FFF

6048K

Reserved

0x10E0 8000

0x10E0 FFFF

32K

L1P RAM/Cache

(1)

L1P RAM/Cache

(1)

L1P RAM/Cache

(1)

0x10E1 0000

0x10F0 3FFF

976K

Reserved

0x10F0 4000

0x10F0 FFFF

48K

L1D RAM

0x10F1 0000

0x10F1 7FFF

32K

L1D RAM/Cache

(1)

L1D RAM/Cache

(1)

L1D RAM/Cache

(1)

0x10F1 8000

0x10FF FFFF

1M-96K

Reserved

0x1100 0000

0x1FFF FFFF

240M

Reserved

0x2000 0000

0x2000 7FFF

32K

DDR2 Control Regs

0x2000 8000

0x2FFF FFFF

256M-32K

Reserved

0x3000 0000

0x3FFF FFFF

256M

PCI Data

0x4000 0000

0x41FF FFFF

32M

Reserved

0x4200 0000

0x43FF FFFF

32M

EMIFA Data (CS2)

(2)

EMIFA Data (CS2)

(2)

0x4400 0000

0x45FF FFFF

32M

EMIFA Data (CS3)

(2)

EMIFA Data (CS3)

(2)

Reserved

0x4600 0000

0x47FF FFFF

32M

EMIFA Data (CS4)

(2)

EMIFA Data (CS4)

(2)

0x4800 0000

0x49FF FFFF

32M

EMIFA Data (CS5)

(2)

EMIFA Data (CS5)

(2)

0x4A00 0000

0x4BFF FFFF

32M

Reserved

0x4C00 0000

0x4FFF FFFF

64M

VLYNQ (Remote Data)

0x5000 0000

0x7FFF FFFF

768M

Reserved

0x8000 0000

0x8FFF FFFF

256M

DDR2 Memory Controller

0x9000 0000

0xFFFF FFFF

1792M

Reserved

(1)

For all boot modes that default to DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,

BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the

bootloader code, all C64x+ memories are configured as all RAM (L2CFG.L2MODE = 0h, L1PCFG.L1PMODE = 0h, and

L1DCFG.L1DMODE = 0h). If cache use is required, the application code must explicitly enable the cache. For more information on boot

modes, see Section 3.4.1 , Boot Modes. For more information on the bootloader, see the Using the TMS320C642x Bootloader

Application Report (literature number SPRAAK5). For the EMIFA ROM Direct Boot (BOOTMODE[3:0] = 0100, FASTBOOT = 0), the

bootloader is not executed—that is, L2 RAM/Cache defaults to all RAM (L2CFG.L2MODE = 0h); L1P RAM/Cache defaults to all cache

(L1PCFG.L1PMODE = 7h); and L1D RAM/Cache defaults to all cache (L1DCFG.L1DMODE = 7h).

(2)

The EMIFA CS0 and CS1 are not functionally supported on the C6424 device, and therefore, are not pinned out.

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