TNETV2664FIBZWT datasheet(73/249 Pages) TI1

73 / 249 page

TMS320C6424

www.ti.com

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 3-5. User-Select Multiplier Fastboot Modes (FASTBOOT = 1)

DEVICE BOOT AND

PLLC1 CLOCK SETTING AT BOOT

CONFIGURATION PINS

C6424 DMP

DSPBOOTADDR

BOOT DESCRIPTION(1)

DEVICE

(Master/Slave)

(DEFAULT)(1)

PLL

CLKDIV1 DOMAIN

BOOTMODE[3:0]

PCIEN

FREQUENCY

MODE(2)

(SYSCLK1 DIVIDER)

(SYSCLK1)

0000

0 or 1

No Boot (Emulation Boot)

Master

Bypass

CLKIN

0x0010 0000

Reserved

–

0001

PCI Boot without Auto

Slave

Table 3-6

0x0010 0000

Initialization

HPI Boot

Slave

Table 3-6

0x0010 0000

0010

PCI Boot with Auto

Slave

Table 3-6

0x0010 0000

Initialization

0011

0 or 1

Reserved

–

EMIFA ROM FASTBOOT

0100

0 or 1

Master

Table 3-6

0x0010 0000

with AIS

I2C Boot

0101

0 or 1

Master

Table 3-6

0x0010 0000

[FAST MODE](3)

16-bit SPI Boot

0110

0 or 1

Master

Table 3-6

0x0010 0000

[McBSP0]

0111

0 or 1

NAND Flash Boot

Master

Table 3-6

0x0010 0000

UART Boot without

1000

0 or 1

Hardware Flow Control

Master

Table 3-6

0x0010 0000

[UART0]

EMIFA ROM FASTBOOT

1001

0 or 1

Master

Table 3-6

–

without AIS

1010

0 or 1

VLYNQ Boot

Slave

x20

CLKIN x20 / 2

0x0010 0000

1011

0 or 1

Reserved

–

1100

0 or 1

Reserved

–

1101

0 or 1

Reserved

–

UART Boot with

1110

0 or 1

Hardware Flow Control

Master

Table 3-6

0x0010 0000

[UART0]

24-bit SPI Boot

1111

0 or 1

Master

x20

CLKIN x20 / 2

0x0010 0000

(McBSP0 + GP[97])

(1)

For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code disables all C64x+ cache (L2, L1P, and L1D)

so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application

code must explicitly enable the cache.For more information on the bootloader, see the Using the TMS320C642x Bootloader Application

Report (literature number SPRAAK5).

(2)

Any supported PLL MODE is available. [See Table 3-6 for supported C6424 PLL MODE options].

(3)

I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is not

available for MXI/CLKIN frequencies less than 21 MHz.

Table 3-6. PLL Multiplier Selection (PLLMS[2:0]) in User-Select Multiplier Fastboot Modes

(FASTBOOT = 1)

DEVICE BOOT AND

PLLC1 CLOCK SETTING AT BOOT

CONFIGURATION PINS

CLKDIV1 DOMAIN

PLLMS[2:0]

PLL MODE

DEVICE FREQUENCY (SYSCLK1)

(SYSCLK1 DIVIDER)

000

x20

CLKIN x20 / 2

001

x15

CLKIN x15 / 2

010

x16

CLKIN x16 / 2

011

x18

CLKIN x18 / 2

100

x22

CLKIN x22 / 2

101

x25

CLKIN x25 / 2

110

x27

CLKIN x27 / 2

111

x30

CLKIN x30 / 2

Device Configurations

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