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TNETV2664FIBZWT 数据表(PDF) 77 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 77 Page - Texas Instruments |
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77 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 For example, if BOOTMODE[3:0] = 0110b, FASTBOOT = 1, the MXI/CLKIN frequency = 30 MHz, PLLMS[2:0] = 100b, the combination of Table 3-5 and Table 3-6 indicates that the device frequency (SYSCLK1) is CLKIN x 22 / 2 = 330 MHz. This means SYSCLK3 frequency is 330 / 6 = 55 MHz, resulting in SPI serial clock frequency of 55 / 3 = 18.3 MHz. 3.4.1.5 Host Boot Modes The C6424 supports two types of host boots—PCI Boot or HPI Boot. The PCI Boot (BOOTMODE[3:0] = 0001b or 0010b, PCIEN = 1) is only available in fastboot (FASTBOOT = 1), as shown in Table 3-5. The HPI Boot is available in fastboot and non-fastboot, as shown in Table 3-4 and Table 3-5. Note: The HPI HSTROBE inactive pulse duration timing requirement [tw(HSTBH)] is dependent on the HPI internal clock source (SYSCLK3) frequency (see Section 6.12.3, HPI Electrical Data/Timing). The external host must be aware of the SYSCLK3 frequency during boot to ensure the HSTROBE pulse duration timing requirement is met. 3.4.2 Bootmode Registers 3.4.2.1 BOOTCFG Register The Device Bootmode (see Section 3.4.1, Boot Modes) and Configuration pins (see Section 3.5.1, Device and Peripheral Configurations at Device Reset) latched at reset are captured in the Device Boot Configuration (BOOTCFG) register which is accessible through the System Module. This is a read-only register. The bits show the values latched from the corresponding configuration pins sampled at device reset. For more information on how these pins are sampled at device reset, see Section 6.5.1.2, Latching Boot and Configuration Pins. For the corresponding device boot and configuration pins, see Table 2-7, BOOT Terminal Functions. 31 21 20 19 18 17 16 LENDI FASTB DPCIE RESERVED RSV 8_16 AN OOT N R-0000 0000 0001 R-L R-L R-0 R-L R-L 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSV PLLMS RSV DAEM RESERVED BOOTMODE R-0 R-LLL R-0 R-LLL R-0000 R-LLLL LEGEND: R = Read only; L = pin state latched at reset rising edge; -n = value after reset Figure 3-2. BOOTCFG Register—0x01C4 0014 Table 3-7. BOOTCFG Register Description Bit Field Name Description 31:21 RESERVED Reserved. Writes have no effect. Little Endian Selection (see Section 3.5.1.4, Endianess Selection (LENDIAN)) This field determines the device endian mode. 20 LENDIAN 0 = Device is Big Endian 1 = Device is Little Endian The default value is latched from LENDIAN configuration pin. Copyright © 2007–2009, Texas Instruments Incorporated Device Configurations 77 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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