TNETV2664FIBZWT datasheet(82/249 Pages) TI1

82 / 249 page

TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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All of the device boot and configuration pin settings are captured in the corresponding bit fields in the

BOOTCFG register (see Section 3.4.2.1, BOOTCFG Register).

The following subsections provide more details on the device configurations determined at device reset:

AEM, PLLMS, PCIEN, 8_16, and LENDIAN.

3.5.1.1

EMIFA CS2 Bus Width (8_16)

The default width of the EMIFA chip select space 2 (EM_CS2) is determined by the 8_16 input captured in

BOOTCFG.8_16. If 8_16 = 0, the EM_CS2 space data bus defaults to 8-bits wide. If 8_16 = 1, it defaults

to 16-bits wide. The C6424 sets the default of the EMIFA register A1CR.ASIZE based on the 8_16 input.

For EMIFA boot modes (Section 3.4.1.3, EMIFA Boot Modes), the user must set 8_16 appropriately to set

the default bus width for boot.

Note: 8_16 only selects the default bus width for EMIFA CS2 space. The CS2 bus width may be changed

at any time by software through programming the EMIFA register A1CR.ASIZE field. All other chip select

spaces default to 8-bits wide and must be modified using the corresponding EMIFA control register if

16-bit operation is desired.

Note: 8_16 does not affect pin mux control. It is the user's responsibility to configure AEM[2:0]

appropriately so that the desired EMIFA data pins are selected.

3.5.1.2

EMIFA Pinout Mode (AEM[2:0])

To support different usage scenarios, the C6424 provides intricate pin multiplexing between the EMIFA

and other peripherals. The PINMUX0.AEM register bit field in the System Module determines the EMIFA

Pinout Mode. The AEM[2:0] pins only select the default EMIFA Pinout Mode. It is latched at device reset

de-assertion (high) into the BOOTCFG.DAEM bit field. The AEM[2:0] value also sets the default of the

PINMUX0.AEM bit field. While the BOOTCFG.DAEM bit field shows the actual latched value and cannot

be modified, the PINMUX0.AEM value can be changed by software to modify the EMIFA Pinout Mode.

Note: The AEM[2:0] value does not affect the operation of the EMIFA module itself. It only affects which

EMIFA pins are brought out to the device pins. For more details on the AEM settings, see Section 3.7,

Multiplexed Pin Configurations.

3.5.1.3

FASTBOOT PLL Multiplier Select (PLLMS)

If FASTBOOT = 1, the PLLMS[2:0] pins select PLL multiplier for Fastboot modes. If FASTBOOT = 0, the

PLLMS[2:0] pins are ignored.

The PLLMS[2:0] pin values are latched at device reset de-assertion into the BOOTCFG.PLLMS field and

cannot be modified by software. This value is only applicable during fast boot.

For more information on boot modes and the FASTBOOT PLL multiplier selection, see Section 3.4.1, Boot

Modes.

3.5.1.4

Endianess Selection (LENDIAN)

The LENDIAN configuration pin latched at reset determines the endianess setting of the device. If

LENDIAN = 1, little endian is selected. If LENDIAN = 0, big endian is selected.

The setting is latched and stored in the BOOTCFG.LENDIAN field and cannot be modified by software.

3.5.1.5

PCI Enable (PCIEN)

The PCIEN configuration pin determines if the PCI peripheral is used on this device. If PCIEN = 1

indicating the PCI is used, then the PCI multiplexed pins default to PCI functions, and the pins’

corresponding internal pullup/pulldown resistors are disabled. If PCIEN = 0 indicating the PCI is not used,

then the PCI muxed pins default to non-PCI functions, and the pins’ corresponding internal

pullup/pulldown resistors are enabled.

Device Configurations

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