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TNETV2664FIBZWT 数据表(PDF) 43 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 43 Page - Texas Instruments |
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43 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 Table 2-14. DDR2 Memory Controller Terminal Functions (continued) SIGNAL OTHER(2) TYPE(1) DESCRIPTION ZWT ZDU (3) NAME NO. NO. DDR_D[31] T19 Y22 DDR_D[30] U19 AA21 DDR_D[29] V18 Y21 DDR_D[28] U18 AB20 DDR_D[27] W17 Y20 DDR_D[26] T18 AA20 DDR_D[25] U17 AB19 DDR_D[24] V17 Y19 DDR_D[23] T17 AA19 DDR_D[22] V16 AB18 DDR_D[21] W16 AB17 DDR_D[20] U15 Y17 DDR_D[19] V15 AA17 DDR_D[18] W15 AB16 DDR_D[17] V14 Y16 DDR_D[16] W14 AA16 DDR2 bi-directional data bus can be configured as 32-bits wide I/O/Z DVDDR2 or 16-bits wide. DDR_D[15] V7 AB6 DDR_D[14] W6 Y6 DDR_D[13] V6 AA6 DDR_D[12] W5 AB5 DDR_D[11] V5 Y5 DDR_D[10] U5 AA5 DDR_D[9] W4 W5 DDR_D[8] V4 AB4 DDR_D[7] W3 W4 DDR_D[6] V3 AB3 DDR_D[5] U3 Y3 DDR_D[4] V2 AA3 DDR_D[3] U2 AA2 DDR_D[2] U1 W2 DDR_D[1] T2 Y2 DDR_D[0] T1 Y1 DDR_VREF T15 W18 I (3) Reference voltage input for the SSTL_18 I/O buffers DDR_VSSDLL T13 W15 GND (3) Ground for the DDR2 DLL DDR_VDDDLL T12 W14 S (3) Power (1.8 Volts) for the DDR2 Digital Locked Loop Impedance control for DDR2 outputs. This must be connected DDR_ZN T10 W12 (3) via a 200- Ω resistor to DVDDR2. Impedance control for DDR2 outputs. This must be connected DDR_ZP T11 W13 (3) via a 200- Ω resistor to VSS. Copyright © 2007–2009, Texas Instruments Incorporated Device Overview 43 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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