TNETV2664FIBZWT datasheet(81/249 Pages) TI1

81 / 249 page

TMS320C6424

www.ti.com

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 3-10. Default Functions Affected by Device Boot and Configuration Pins

DEVICE BOOT AND

BOOT SELECTED

PIN MUX CONTROL

GLOBAL SETTING

PERIPHERAL SETTING

CONFIGURATION PINS

BOOTMODE[3:0]

Boot Mode

PINMUX0/PINMUX1

I/O Pin Power:

PSC/Peripherals:

Registers:

Based on

BOOTMODE[3:0], the

bootloader code programs bootloader code programs

bootloader code programs VDD3P3V_PWDN register the PSC to put

PINMUX0 and PINMUX1

to power up the I/O pins

boot-related peripheral(s)

registers to select the

required for boot.

in the Enable State, and

appropriate pin functions

programs the peripheral(s)

required for boot.

for boot operation.

FASTBOOT

Fastboot

–

Sets Device Frequency:

–

Based on BOOTMODE,

FASTBOOT, and PLLMS;

the bootloader code

programs PLLC1.

PLLMS[2:0]

If FASTBOOT = 1, the

–

Sets Device Frequency:

–

PLLMS[2:0] selects the

Based on BOOTMODE,

FASTBOOT PLL

FASTBOOT, and PLLMS;

Multiplier.

the bootloader code

programs PLLC1.

AEM[2:0]

–

PINMUX0.AEM:

–

PSC/EMIFA:

Sets the default of this

The EMIFA module state

field to control the EMIFA

defaults to SwRstDisable

Pinout Mode.

if AEM = 0; otherwise, the

EMIFA module state

Affects the pin muxing in

defaults to Enable.

EMIFA Sub-Block 0, 1,

and 3.

8_16

EMIFA Boot:

–

EMIFA:

8_16 determines the

Sets default of register

EMIFA CS2 Data Bus

field A1CR.ASIZE to

Width.

determine the default data

bus width for EMIFA CS2

space.

PCIEN(1)

Host Boot:

PINMUX1.PCIEN:

–

PSC/Peripheral

PCIEN selects the type of

sets this field to control

(Applicable to Host Boot

Host Boot

the PCI pin muxing in

only):

(HPI Boot or PCI Boot)

Host Block, PCI Data

Based on the Host Boot

Block, GPIO Block,

type (PCI or HPI), the

EMIFA Sub-Block 0 and

bootloader code programs

Sub-Block 3.

the PSC to put the

(1) (2)

corresponding peripheral

in the Enable State, and

programs the peripheral

for boot operation.

LENDIAN

–

Device endianess

–

(1)

Software can modify all PINMUX0 and PINMUX1 bit fields from their defaults, except for PINMUX1.PCIEN.

(2)

In addition to pin mux control, PCIEN also affects the internal pullup/down resistors of the PCI capable pins. When PCIEN = 0, internal

pullup/down resistors on the PCI capable pins are enabled. When PCIEN = 1, internal pullup/down resistors on the PCI capable pins are

disabled to be compliant to the PCI Local Bus Specification Revision 2.3.

For proper device operation, external pullup/pulldown resistors may be required on these device boot and

configuration pins. For discussion situations where external pullup/pulldown resistors are required, see

Section 3.9.1, Pullup/Pulldown Resistors.

Note: Except for PCIEN, all other C6424 configuration inputs (BOOTMODE[3:0], FASTBOOT,

PLLMS[2:0], AEM[2:0], 8_16, and LENDIAN) are multiplexed with other functional pins. These pins

function as device boot and configuration pins only during device reset. The user must take care of any

potential data contention in the system. To help avoid system data contention, the C6424 puts these

configuration pins into a high-impedance state (Hi-Z) when device reset (RESET or POR) is asserted, and

continues to hold them in a high-impedance state until the internal global reset is removed; at which point,

the default peripheral (either GPIO or EMIFA based on default of AEM[2:0]) will now control these pins.

Device Configurations

Submit Documentation Feedback

Product Folder Link(s): TMS320C6424

TNETV2664FIBZWT 数据表(PDF) 81 Page - Texas Instruments

TNETV2664FIBZWT 数据表(HTML) 81 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载