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TNETV2664FIBZWT 数据表(PDF) 83 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 83 Page - Texas Instruments |
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83 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 The PCIEN setting is captured and stored in the BOOTCFG.DPCIEN bit field, and also in the PINMUX1.PCIEN bit field. These values cannot be changed by software. Furthermore, for proper device operation, the user must hold the desired setting at the PCIEN pin throughout device operation. 3.6 Configurations After Reset The following sections provide details on configuring the device after reset. Multiplexed pins are configured both at and after reset. Section 3.5.1, Device and Peripheral Configurations at Device Reset, discusses multiplexed pin control at reset. For more details on multiplexed pins control after reset, see Section 3.7 , Multiplexed Pin Configurations. 3.6.1 Switch Central Resource (SCR) Bus Priorities Prioritization within the Switched Central Resource (SCR) is programmable for each master. The register bit fields and default priority levels for C6424 bus masters are shown in Table 3-11, C6424 Default Bus Master Priorities. The priority levels should be tuned to obtain the best system performance for a particular application. Lower values indicate higher priority. For most masters, their priority values are programmed at the system level by configuring the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1 registers are shown in Figure 3-5 and Figure 3-6. The C64x+ and EDMA masters contain registers that control their own priority values. Table 3-11. C6424 Default Bus Master Priorities Priority Bit Field Bus Master Default Priority Level EDMATC0P EDMATC0 0 (EDMACC QUEPRI Register) EDMATC1P EDMATC1 0 (EDMACC QUEPRI Register) EDMATC2P EDMATC2 0 (EDMACC QUEPRI Register) C64X+_DMAP C64X+ (DMA) 7 (C64x + MDMAARBE.PRI field) C64X+_CFGP C64X+ (CFG) 1 (MSTPRI0 Register) EMACP EMAC 4 (MSTPRI1 Register) VLYNQP VLYNQ 4 (MSTPRI1 Register) HPIP HPI 4 (MSTPRI1 Register) PCIP PCI 4 (MSTPRI1 Register) 31 16 RESERVED R-0000 0000 0000 0000 15 11 10 9 8 7 0 RESERVED C64X+_CFGP RESERVED R-0000 0 R/W-001 R-0000 0000 LEGEND: R = Read; W = Write; -n = value after reset Figure 3-5. MSTPRI0 Register— 0x01C4 003C Table 3-12. MSTPRI0 Register Description Bit Field Name Description 31:11 RESERVED Reserved. Read-only, writes have no effect. Copyright © 2007–2009, Texas Instruments Incorporated Device Configurations 83 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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