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TNETV2664FIBZWT 数据表(PDF) 78 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 78 Page - Texas Instruments |
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78 / 249 page  TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com Table 3-7. BOOTCFG Register Description (continued) Bit Field Name Description Fastboot (see Section 3.4.1.1, FASTBOOT) This field is used by the device bootloader code to determine if it needs to speed up the device to PLL mode before booting. 19 FASTBOOT 0 = No Fastboot 1 = Fastboot The default value is latched from FASTBOOT configuration pin. 18 RSV Reserved. Writes have no effect. PINMUX1.PCIEN Default (see Section 3.5.1.5, PCI Enable) For more details on the PCIEN settings, see Section 3.7.2.2, PINMUX1 Register Description. This field affects the pin mux control by setting the default of PINMUX1.PCIEN. This field determines if the internal pullup/pulldown resistors on the PCI capable pins are enabled/disabled. This field does not affect PCI 17 DPCIEN register setting. The user must keep the value on the PCIEN pin constant throughout the operation. The default value is from the PCIEN configuration pin. EMIFA CS2 Bus Width Default Configuration ( see Section 3.5.1.1, EMIFA CS2 Bus Width (8_16)) 0 = EMIFA CS2 space defaults to 8-bit data bus width 1 = EMIFA CS2 space defaults to 16-bit bus width 16 8_16 This field does not affect pin mux control. This field affects the EMIFA register setting—the default of EMIFA register field A1CR.ASIZE is set to this 8_16 value. The default value is latched from the 8_16 configuration pin. 15 RSV Reserved. Writes have no effect. Fastboot PLL Multiplier Select [PLLMS] (see Section 3.5.1.3, Fast Boot PLL Multiplier Select [PLLMS]) 14:12 PLLMS If FASTBOOT = 1, this field selects the FASTBOOT PLL Multiplier according to Table 3-6. The default value is latched from the PLLMS[2:0] configuration pins. 11 RSV Reserved. Writes have no effect. PINMUX0.AEM default [DAEM] (see Section 3.5.1.2, EMIFA Pinout Mode (AEM[2:0])) For more details on the AEM settings, see Section 3.7.2.1, PINMUX0 Register Description. 10:8 DAEM This field affects pin mux control by setting the default of PINMUX0.AEM. This field does not affect EMIFA Register settings. The default value is latched from the AEM[2:0] configuration pins. 7:4 RESERVED Reserved. Writes have no effect. Boot Mode (see Section 3.4.1, Boot Modes) 3:0 BOOTMODE This field is used in conjunction with FASTBOOT, PCIEN, and PLLMS to determine the device boot mode. The default value is latched from the BOOTMODE[3:0] configuration pins. 3.4.2.2 BOOTCMPLT Register If the bootloader code detects an error during boot, it records the error status in the Boot Complete (BOOTCMPLT) register. In addition, the BOOTCMPLT register is used for communication between the external host and the bootloader code during a Host Boot (PCI Boot or HPI boot). Once the external host has completed boot, it must perform the following communication with the bootloader code: • Write the desired 32-bit CPU starting address in the DSPBOOTADDR register (see Section 3.4.2.3, DSPBOOTADDR Register). 78 Device Configurations Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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