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TNETV2664FIBZWT 数据表(PDF) 90 Page - Texas Instruments

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部件名 TNETV2664FIBZWT
功能描述  Fixed-Point Digital Signal Processor
PDF  249 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV2664FIBZWT 数据表(HTML) 90 Page - Texas Instruments

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TMS320C6424
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
www.ti.com
register format is shown in Figure 3-11 and the bit field descriptions are given in Table 3-17. Some muxed
pins are controlled by more than one PINMUX bit field. For the combination of the PINMUX bit fields that
control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on C6424. For more information on EMIFA
Block pin muxing, see Section 3.7.3.13, EMIFA Block Muxing. For the pin-by-pin muxing control of the
EMIFA Block, see Section 3.7.3.13.2, EMIFA Block Pin-By-Pin Multiplexing Summary.
Note: In addition to PINMUX0 bit fields, the EMIFA Block also requires the PCIEN bit in the Pin
Multiplexing 1 Register (PINMUX1, Section 3.7.2.2) to determine the PCI settings.
31
18
17
16
RESERVED
R/W-0000 0000 0000 0XXX
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CS3S
CS4S
CS5S
RESERVED
RSV
RSV
RESERVED
RMII
AEM
EL
EL
EL
R/W-0000 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-00
R/W-0
R/W-LLL
LEGEND: R/W = Read/Write; R = Read only; L = pin state latched at reset rising edge; -n = value after reset
(1) For proper C6424 device operation, always write a value of "0" to all RESERVED/RSV bits.
(2) PINMUX0 bits 18:16 are reserved/ don't care. These bits may default to non-zero values.
Figure 3-11. PINMUX0 Register—0x01C4 0000 (1) (2)
Table 3-17. PINMUX0 Register Description
Bit
Field Name
Description
Pins Controlled
Reserved. For proper device operation, the user should only write "0" to this bit
31:11
RESERVED
(default).
Sub-Block 1
Chip Select 3 Select.
EM_CS3/GP[13]
10
CS3SEL
0 = GPIO pin GP[13] (default)
The PINMUX0 field CS3SEL alone controls the
1 = EMIFA Chip Select 3 (EM_CS3)
muxing of this pin.
Reserved. For proper device operation, the user should only write "0" to this bit
9
RSV
(default).
Chip Select 4 Select.
Sub-Block 1
0 = GPIO pin GP[32] (default) or RMII RMRXD0. Pin function determined by
RMRXD0/EM_CS4/GP[32]
8
CS4SEL
PINMUX0.RMII.
The combination of PINMUX0 fields CS4SEL
1 = EMIFA Chip Select 4 (EM_CS4). PINMUX0.RMII must be set to 0.
and RMII controls the muxing of this pin.
Reserved. For proper device operation, the user should only write "0" to this bit
7
RSV
(default).
Chip Select 5 Select.
Sub-Block 1
0 = GPIO pin GP[33] (default) or RMII RMRXD1. Pin function determined by
RMRXD1/EM_CS5/GP[33]
6
CS5SEL
PINMUX0.RMII.
The combination of PINMUX0 fields CS5SEL
1 = EMIFA Chip Select 5 (EM_CS5). PINMUX0.RMII must be set to 0.
and RMII controls the muxing of this pin.
Reserved. For proper device operation, the user should only write "0" to this bit
5:4
RESERVED
(default).
RMII Select.
0 = No RMII in EMIFA Block
RMRXER/GP[52]
Field CS5SEL determines function of pin EM_CS5.
RMRXD1/EM_CS5/GP[33]
Field CS4SEL determines function of pin EM_CS4.
RMRXD0/EM_CS4/GP[32]
The remaining 6 pins function as GP[52] and GP[31:27].
REFCLK/GP[31]
RMCRSDV/GP[30]
1 = RMII in EMIFA Block
RMTXEN/GP[29]
3
RMII
These 8 pins function as RMII pins: RMRXER, RMRXD1, RMRXD0, REFCLK,
RMTXD0/GP[28]
RMCRSDV, RMTXEN, RMTXD0, and RMTXD1.
RMTXD1/GP[27]
When EMAC (RMII) is selected, EMAC(MII) must not be selected.
PINMUX1.HOSTBK must not be set to 011b or 100b.
The pin mux for these pins are controlled by a
CS4SEL and CS5SEL must be programmed to 0.
combination of PINMUX0 fields RMII, CS4SEL,
and CS5SEL.
If EMAC operation is desired, EMAC must be placed in reset before
programming PINMUX0.RMII or PINMUX1.HOSTBK to select EMAC pins.
90
Device Configurations
Copyright © 2007–2009, Texas Instruments Incorporated
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Product Folder Link(s): TMS320C6424



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