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TNETV2664FIBZWT 数据表(PDF) 35 Page - Texas Instruments

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部件名 TNETV2664FIBZWT
功能描述  Fixed-Point Digital Signal Processor
PDF  249 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV2664FIBZWT 数据表(HTML) 35 Page - Texas Instruments

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TMS320C6424
www.ti.com
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010)
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
ZWT
ZDU
NAME
NO.
NO.
EMIFA FUNCTIONAL PINS: 16-Bit ASYNC/NOR (EMIFA Pinout Mode 2, AEM[2:0] = 010)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., PCIEN, AEM[2:0], etc.). For more details, see
Section 3.7, Multiplexed Pin Configurations.
This pin is multiplexed between EMIFA, and GPIO.
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
asynchronous memories (i.e., NOR flash).
EM_CS2/
IPD
This is the chip select for the default boot and ROM boot modes.
C19
C22
I/O/Z
GP[12]
DVDD33
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMIFA, and GPIO.
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
asynchronous memories (i.e., NOR flash).
EM_CS3/
IPD
C18
D22
I/O/Z
GP[13]
DVDD33
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA, and GPIO.
For EMIFA, it is Chip Select 4 output EM_CS4 for use with
RMRXD0/
asynchronous memories (i.e., NOR flash).
IPD
EM_CS4/
E19
H22
I/O/Z
DVDD33
Note: This pin features an internal pulldown (IPD). If this pin is
GP[32]
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA, and GPIO.
For EMIFA, it is Chip Select 5 output EM_CS5 for use with
RMRXD1/
asynchronous memories (i.e., NOR flash).
IPD
EM_CS5/
F19
J22
I/O/Z
DVDD33
Note: This pin features an internal pulldown (IPD). If this pin is
GP[33]
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMIFA and GPIO.
EM_R/W/
IPD
D13
C17
I/O/Z
GP[35]
DVDD33
For EMIFA, it is read/write output EM_R/W.
EM_WAIT/
IPU
For EMIFA (ASYNC/NOR), this pin is wait state extension input
E15
D20
I/O/Z
(RDY/BSY)
DVDD33
EM_WAIT.
IPU
EM_OE
D15
D19
I/O/Z
For EMIFA, it is output enable output EM_OE.
DVDD33
IPU
EM_WE
E14
C19
I/O/Z
For EMIFA, it is write enable output EM_WE.
DVDD33
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, this is the Bank Address 0 output (EM_BA[0]).
EM_BA[0]/
IPD
When connected to an 8-bit asynchronous memory, this pin is the
C17
E20
I/O/Z
GP[6]/(AEM1)
DVDD33
lowest order bit of the byte address.
When connected to a 16-bit asynchronous memory, this pin has the
same function as EMIFA address pin 22 (EM_A[22]).
(1)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2)
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1 , Pullup/Pulldown Resistors.
(3)
Specifies the operating I/O supply voltage for each signal.
Copyright © 2007–2009, Texas Instruments Incorporated
Device Overview
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