TNETV2664FIBZWT datasheet(37/249 Pages) TI1

37 / 249 page

TMS320C6424

www.ti.com

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010) (continued)

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[6]/AD20/

IPD

B10

I/O/Z

GP[95]

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 6 output EM_A[6].

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[5]/AD19/

IPD

A10

I/O/Z

GP[96]

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 5 output EM_A[5].

This pin is multiplexed between EMIFA and GPIO.

EM_A[4]/

IPD

A17

B21

I/O/Z

GP[10]/(PLLMS2)

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 4 output EM_A[4].

This pin is multiplexed between EMIFA and GPIO.

EM_A[3]/

IPD

B18

D21

I/O/Z

GP[11]

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 3 output EM_A[3].

This pin is multiplexed between EMIFA and GPIO.

EM_A[2]/(CLE)/

IPD

B16

A20

I/O/Z

GP[8]/(PLLMS0)

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address bit 2 output EM_A[2].

This pin is multiplexed between EMIFA and GPIO.

EM_A[1]/(ALE)/

IPD

A16

B20

I/O/Z

GP[9]/(PLLMS1)

DVDD33

For EMIFA (AEM[2:0] = 010), this pin is address output EM_A[1].

This pin is multiplexed between EMIFA and GPIO.

For EMIFA (AEM[2:0] = 010), this pin is address output EM_A[0],

which is the least significant bit on a 32-bit word address.

EM_A[0]/

IPD

B17

C21

I/O/Z

For an 8-bit asynchronous memory, this pin is the 3rd bit of the

GP[7]/(AEM2)

DVDD33

address.

When connected to a 16-bit asynchronous memory, this pin is the 2nd

bit of the address.

EM_D0/

IPD

D16

E21

I/O/Z

GP[14]

DVDD33

EM_D1/

IPD

D18

G20

I/O/Z

GP[15]

DVDD33

EM_D2/

IPD

D17

E22

I/O/Z

GP[16]

DVDD33

EM_D3/

IPD

E16

F20

I/O/Z

GP[17]

DVDD33

EM_D4/

IPD

E18

G21

I/O/Z

GP[18]

DVDD33

EM_D5/

IPD

E17

F22

I/O/Z

GP[19]

DVDD33

EM_D6/

IPD

F16

F21

I/O/Z

GP[20]

DVDD33

EM_D7/

IPD

These pins are multiplexed between EMIFA and GPIO.

F17

H20

I/O/Z

GP[21]

DVDD33

For EMIFA (AEM[2:0] = 010), these pins are the 16-bit bi-directional

EM_D8/

IPD

A12

A15

I/O/Z

data bus (EM_D[15:0]).

GP[43]

DVDD33

EM_D9/

IPD

B13

B15

I/O/Z

GP[42]

DVDD33

EM_D10/

IPD

C13

B16

I/O/Z

GP[41]

DVDD33

EM_D11/

IPD

D14

C18

I/O/Z

GP[40]

DVDD33

EM_D12/

IPD

B14

A16

I/O/Z

GP[39]

DVDD33

EM_D13/

IPD

C14

B17

I/O/Z

GP[38]

DVDD33

EM_D14/

IPD

B15

B18

I/O/Z

GP[37]

DVDD33

EM_D15/

IPD

C15

B19

I/O/Z

GP[36]

DVDD33

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