TNETV2664FIBZWT datasheet(76/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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3.4.1.4.1 I2C Boot

If FASTBOOT = 0, then I2C Boot (BOOTMODE = 0101) is performed in Standard-Mode (up-to 100 kbps).

If FASTBOOT = 1, then I2C Boot is performed in Fast-Mode (up-to 400 kbps). The actual I2C data

transfer rate is dependent on the MXI/CLKIN frequency.

This is how the bootloader programs the I2C:

•

I2C Boot in Fast-Mode (BOOTMODE[3:0] = 0101b, FASTBOOT = 1)

–

I2C register settings: ICPSC.IPSC = 210, ICCLKL.ICCL = 810, ICCKH.ICCH = 810

–

Resulting in the following I2C prescaled module clock frequency (internal I2C clock):

•

(CLKIN frequency in MHz) / 3

–

Resulting in the following I2C serial clock (SCL):

•

SCL frequency (in kHz) = (CLKIN frequency in MHz) / 78 * 1000

•

SCL low pulse duration (in

μs) = 39 / (CLKIN frequency in MHz)

•

SCL high pulse duration (in

μs) = 39 / (CLKIN frequency in MHz)

•

I2C Boot in Standard-Mode (BOOTMODE[3:0] = 0101b, FASTBOOT = 0)

–

I2C register settings: ICPSC.IPSC = 210, ICCLKL.ICCL = 4510, ICCKH.ICCH = 4510

–

Resulting in the following I2C prescaled module clock frequency (internal I2C clock):

•

(CLKIN frequency in MHz) / 3

–

Resulting in the following I2C serial clock (SCL):

•

SCL frequency (in kHz) = (CLKIN frequency in MHz) / 300 * 1000

•

SCL low pulse duration (in

μs) = 150 / (CLKIN frequency in MHz)

•

SCL high pulse duration (in

μs) = 150 / (CLKIN frequency in MHz)

Note: the I2C peripheral requires that the prescaled module clock frequency must be between 7 to 12

MHz. Therefore, the I2C boot is only available for MXI/CLKIN frequency between 21 MHz and 30 MHz.

For more details on the I2C peripheral configurations and clock requirements, see the TMS320C642x DSP

Inter-Integrated Circuit (I2C) Peripheral User’s Guide (literature number SPRUEN0).

3.4.1.4.2 UART Boot

For UART Boot (BOOTMODE[3:0] = 1000b or 1110b), the bootloader programs the UART0 peripheral as

follows:

•

UART0 divisor is set to 1510

•

Resulting in this UART0 baud rate in kilobit per second (kbps):

–

(CLKIN frequency in MHz) * 1000 / (15 * 16)

The user is responsible for ensuring the resulting baud rate is appropriate for the system. The UART0

divisor (/15) is optimized for CLKIN frequency between 27 to 29 MHz to stay within 5% of the 115200-bps

baud rate.

For more details on the UART peripheral configurations and clock generation, see the TMS320C642x

DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guide (literature number SPRUEN6).

3.4.1.4.3 SPI Boot

Both 16-bit address SPI Boot (BOOTMODE = 0110) and 24-bit address SPI boot are performed through

the McBSP0 peripheral. The bootloader programs the McBSP0 peripheral as follows:

•

McBSP0 register settings: SRGR.CLKGDV = 210

•

Resulting in this SPI serial clock frequency:

–

(SYSCLK3 frequency in MHz) / 3

SYSCLK3 frequency = SYSCLK1 frequency / 6. SYSCLK1 frequency during boot can be found in

Table 3-4, Table 3-5, and/or Table 3-6 based on the boot mode selection.

Device Configurations

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