TNETV2664FIBZWT datasheet(80/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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Table 3-9. DSPBOOTADDR Register Description

Bit

Field Name

Description

DSP Boot Address

After boot, the C64x+ CPU begins execution from this 32-bit address location

0x0010 0000 (for Internal Bootloader ROM).

0x4200 0000 (for EMIFA CS2 Space).

31:0

DSPBOOTADDR

The lower 10 bits (bits 9:0) should always be programmed to "0" as they are ignored by the

C64x+.

Default depends on boot mode selected.

See Table 3-4, Non-Fastboot Modes and Table 3-5, User-Select Multiplier Fastboot Modes.

At device reset, the Boot Controller defaults DSPBOOTADDR to one of two values (either Internal

Bootloader ROM at address 0x0010 0000 or EMIFA CS2 Space 0x4200 0000) based on the boot mode

selected (for the boot mode selections, see Table 3-4 and Table 3-5).

For Non-Host Boot Modes, software can leave the DSPBOOTADDR register at default.

For Host Boots (HPI Boot or PCI Boot), the DSPBOOTADDR register is also used for communication

between the Host and the bootloader code during boot. For Host Boots, the DSPBOOTADDR register

defaults to Internal Bootloader ROM, and the C64x+ CPU is immediately released from reset so that it can

begin executing the bootloader code in this internal ROM. The bootloader code waits for the Host to boot

the device. Once the Host is done booting the device, it must write a new starting address into the

DSPBOOTADDR register, and follow with writing BOOTCMPLT.BC = 1 to indicate the boot is complete.

As soon as the bootloader code detects BOOTCMPLT.BC = 1, it instructs the CPU to jump to this new

DSPBOOTADDR address. At this point, the CPU continues the rest of the code execution starting from

the new DSPBOOTADDR location and the boot is completed.

3.5

Configurations At Reset

Some device configurations are determined at reset. The following subsections give more details.

3.5.1

Device and Peripheral Configurations at Device Reset

Table 2-7, BOOT Terminal Functions, lists the device boot and configuration pins that are latched at

device reset for configuring basic device settings for proper device operation. Table 3-10 summarizes the

device boot and configuration pins, and the device functions that they affect.

Device Configurations

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