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TNETV2664FIBZWT 数据表(PDF) 88 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 88 Page - Texas Instruments |
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88 / 249 page  HostBlock(27pins) (A)(C) PCI(27) PCIEN=1 HOSTBK=000 GPIO(27) PCIEN=0 HOSTBK=000 VLYNQ (10) GPIO(17) VLYNQ (10) EMAC(MII) (15) MDIO (2) PCIEN=0 HOSTBK=001 PCIEN=0 HOSTBK=010 PCIEN=0 HOSTBK=011 PCIEN=0 HOSTBK=100 HPI(26) GPIO(1) MDIO (2) GPIO(10) GPIOBlock(4pins) (C) PCI (4) PCIEN=1 GPIO (4) PCIEN=0 UART0DataBlock(2pins) GPIO(2) UR0DBK=0 UART Data(2) UR0DBK=1 UART0FlowControlBlock(2pins) GPIO(2) UR0FCBK=00 UART0 FlowCtrl(2) UR0FCBK=01 PWM0(1) UR0FCBK=10 GPIO(1) Timer1Block(2pins) GPIO(2) TIM1BK=00 Timer1 (2) TIM1BK=01 UART1 Data(2) TIM1BK=10 Timer0Block(2pins) (D)(E) GPIO(2) TIM0BK=00 Timer0 (2) TIM0BK=01 McBSP0 CLKS0(1) TIM0BK=10 McBSP1 CLKS1(1) McBSP0 CLKS0(1) TIM0BK=11 Timer0 TINPOL (1) PWM1Block(1pin) GPIO (1) PWM1BK=0 PWM1 (1) PWM1BK=1 CLKOUTBlock(1pin) GPIO (1) CKOBK=00 CLKOUT (1) CKOBK=01 PWM2 (1) CKOBK=10 SerialPortSub-Block0(6pins) (D) GPIO(6) SPBK0=00 McBSP0 (6) SPBK0=01 McASP0Receive and3Serializers(6) SPBK0=10 SerialPortSub-Block1(6pins) (E) GPIO(6) SPBK1=00 McBSP1 (6) SPBK1=01 McASP0 Transmitand 1Serializer(6) SPBK1=10 McBSP1 Transmit(3) SPBK1=11 McASP0 SPDIF(3) EMIFA Block(61pins) (A)(B)(C) MajorConfig Option A GPIO MajorConfig OptionB EMAC(RMII) MajorConfig OptionC GPIO EMIFA (Async) Pinout Mode2 32MBper CS PCIDataBlock(3pins) (C) PCI(3) Notmuxed AEM=000, PCIEN=0 RMII=0 AEM=000, PCIEN=0 RMII=1 AEM=010, PCIEN=0 RMII=0 GPIO MajorConfig OptionD GPIO EMIFA (Async) Pinout Mode2 32MBper CS AEM=010, PCIEN=0 RMII=1 EMAC(RMII) MajorConfig OptionE GPIO 8bEMIFA (NAND) Pinout Mode5 AEM=101, PCIEN=0 RMII=0 MajorConfig OptionF GPIO 8bEMIFA (NAND) Pinout Mode5 AEM=101, PCIEN=0 RMII=1 EMAC(RMII) MajorConfig OptionG GPIO PCI AEM=000, PCIEN=1 RMII=0 MajorConfig OptionH GPIO PCI AEM=000, PCIEN=1 RMII=1 EMAC(RMII) MajorConfig OptionJ GPIO 8bEMIFA (NAND) Pinout Mode5 AEM=101, PCIEN=1 RMII=0 PCI MajorConfig OptionK GPIO 8bEMIFA (NAND) Pinout Mode5 AEM=101, PCIEN=1 RMII=1 PCI EMAC(RMII) EMAC(MII) (15) TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com A. Default settings for PINMUX0 and PINMUX1 registers are underlined. B. EMIFA Block: This figure only shows the Major Config Options in the EMIFA Block based on the AEM, RMII, and PCIEN settings. Actual pin functions in the EMIFA Block are further determined by other PINMUX fields. C. PCI pins span multiple blocks (Host Block, GPIO Block, EMIFA Block, and PCI Data Block). For PCI to be operational, PCI pins must be selected in all of these Pin Mux Blocks. For the EMIFA Block, PCI is only supported if AEM = 000b or 101b. D. McBSP0 pins span multiple blocks (Serial Port Sub-Block0 and Timer0 Block). Serial Port Sub-Block0 contains most of the pins needed for McBSP0 operation. Timer0 Block contains the optional external clock source input CLKS0. E. McBSP1 spans multiple blocks (Serial Port Sub-Block1, Timer0 Block). Serial Port Sub-Block1 contains most of the pins needed for McBSP1 operation. Timer0 Block contains the optional external clock source input CLKS1. Figure 3-10. Pin Mux Block Selection 88 Device Configurations Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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