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TNETV2664FIBZWT 数据表(PDF) 68 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 68 Page - Texas Instruments |
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68 / 249 page  TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com Most C6424 3.3-V I/Os can be powered-down to reduce power consumption. The VDD3P3V_PWDN register in the System Module (see Figure 3-1) is used to selectively power down unused 3.3-V I/O pins. For independent control, the 3.3-V I/Os are separated into functional groups—most of which are named according to the pin multiplexing groups (see Table 3-2). For these I/O groups, only the I/O buffers needed for Host/EMIFA Boot or Power-Up Operations are powered up by default (CLKOUT Block, EMIFA Block, Host Block, PCI Data Block, and GPIO Block). Note: To save power, all other I/O buffers are powered down by default. Before using these pins, the user must program the VDD3P3V_PWDN register to power up the corresponding I/O buffers. For a list of multiplexed pins on the device and the pin mux group each pin belongs to, see Section 3.7.3.1, Multiplexed Pins on C6424. Note: The VDD3P3V_PWDN register only controls the power to the I/O buffers. The Power and Sleep Controller (PSC) determines the clock/power state of the peripheral. 31 16 RESERVED R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PCIDA EMBK UR0F UR0D TIMER TIMER SP PWM1 GPIO HOST EMBK EMBK EMBK CLKO T 3 C AT 1 0 2 1 0 UT R-00 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 3-1. VDD3P3V_PWDN Register— 0x01C4 0048 Table 3-2. VDD3P3V_PWDN Register Bit Descriptions(1) BIT NAME DESCRIPTION 31:14 RESERVED Reserved. Read-only, writes have no effect. PCI Data Block I/O Power Down Control. Controls the power of the 3 I/O pins in the PCI Data Block. 13 PCIDAT 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). EMIFA Sub-Block 3 I/O Power Down Control. Controls the power of the 8 I/O pins in the EMIFA Sub-Block 3. 12 EMBK3 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). UART0 Flow Control Block I/O Power Down Control. Controls the power of the 2 I/O pins in the UART0 Flow Control Block. 11 UR0FC 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. UART0 Data Block I/O Power Down Control. Controls the power of the 2 I/O pins in the UART0 Data Block. 10 UR0DAT 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. Timer1 Block I/O Power Down Control. Controls the power of the 2 I/O pins in the Timer1 Block. 9 TIMER1 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. (1) For more details on I/O pins belonging to each pin mux block, see Section 3.7 , Multiplexed Pin Configurations. 68 Device Configurations Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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