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TNETV2664FIBZWT 数据表(PDF) 39 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 39 Page - Texas Instruments |
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39 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010) (continued) SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION ZWT ZDU NAME NO. NO. EM_D0/ IPD D16 E21 I/O/Z GP[14] DVDD33 EM_D1/ IPD D18 G20 I/O/Z GP[15] DVDD33 EM_D2/ IPD D17 E22 I/O/Z GP[16] DVDD33 EM_D3/ IPD E16 F20 I/O/Z GP[17] DVDD33 EM_D4/ IPD E18 G21 I/O/Z GP[18] DVDD33 EM_D5/ IPD E17 F22 I/O/Z GP[19] DVDD33 EM_D6/ IPD F16 F21 I/O/Z GP[20] DVDD33 EM_D7/ IPD These pins are multiplexed between EMIFA (NAND) and GPIO. F17 H20 I/O/Z GP[21] DVDD33 For EMIFA (NAND) AEM[2:0] = 010, these are the 16-bit bi-directional EM_D8/ IPD A12 A15 I/O/Z data bus (EM_D[15:0]). GP[43] DVDD33 EM_D9/ IPD B13 B15 I/O/Z GP[42] DVDD33 EM_D10/ IPD C13 B16 I/O/Z GP[41] DVDD33 EM_D11/ IPD D14 C18 I/O/Z GP[40] DVDD33 EM_D12/ IPD B14 A16 I/O/Z GP[39] DVDD33 EM_D13/ IPD C14 B17 I/O/Z GP[38] DVDD33 EM_D14/ IPD B15 B18 I/O/Z GP[37] DVDD33 EM_D15/ IPD C15 B19 I/O/Z GP[36] DVDD33 Copyright © 2007–2009, Texas Instruments Incorporated Device Overview 39 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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