TNETV2664FIBZWT datasheet(53/249 Pages) TI1

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TMS320C6424

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SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 2-21. Multichannel Audio Serial Port (McASP0) Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

McASP0

AMUTEIN0/FSX1/

IPD

This pin is multiplexed between McASP0, McBSP1, and GPIO.

I/O/Z

GP[109]

DVDD33

For McASP0, it is McASP0 mute input AMUTEIN0 (I).

AMUTE0/DR1/

IPD

This pin is multiplexed between McASP0, McBSP1, and GPIO.

I/O/Z

GP[110]

DVDD33

For McASP0, it is McASP0 mute output AMUTE0 (O/Z).

ACLKR0/CLKX0/

IPD

This pin is multiplexed between McASP0, McBSP0, and GPIO.

I/O/Z

GP[99]

DVDD33

For McASP0, it is McASP0 receive bit clock ACLKR0 (I/O/Z).

This pin is multiplexed between McASP0, McBSP0, and GPIO.

AHCLKR0/CLKR0/

IPD

I/O/Z

For McASP0, it is McASP0 receive high-frequency master clock

GP[101]

DVDD33

AHCLKR0 (I/O/Z).

ACLKX0/CLKX1/

IPD

This pin is multiplexed between McASP0, McBSP1, and GPIO.

I/O/Z

GP[106]

DVDD33

For McASP0, it is McASP0 transmit bit clock ACLKX0 (I/O/Z).

This pin is multiplexed between McASP0, McBSP1, and GPIO.

AHCLKX0/CLKR1/

IPD

I/O/Z

For McASP0, it is McASP0 transmit high-frequency master clock

GP[108]

DVDD33

AHCLKX0 (I/O/Z).

This pin is multiplexed between McASP0, McBSP0, and GPIO.

AFSR0/DR0/

IPD

I/O/Z

For McASP0, it is McASP0 receive frame synchronization AFSR0

GP[100]

DVDD33

(I/O/Z).

This pin is multiplexed between McASP0, McBSP1, and GPIO.

AFSX0/DX1/

IPD

I/O/Z

For McASP0, it is McASP0 transmit frame synchronization AFSX0

GP[107]

DVDD33

(I/O/Z).

This pin is multiplexed between McASP0, McBSP0, and GPIO.

AXR0[3]/FSR0/

IPD

I/O/Z

For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 3

GP[102]

DVDD33

AXR0[3] (I/O/Z).

This pin is multiplexed between McASP0, McBSP0, and GPIO.

AXR0[2]/FSX0/

IPD

I/O/Z

For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 2

GP[103]

DVDD33

AXR0[2] (I/O/Z).

This pin is multiplexed between McASP0, McBSP0, and GPIO.

AXR0[1]/DX0/

IPD

I/O/Z

For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 1

GP[104]

DVDD33

AXR0[1] (I/O/Z).

This pin is multiplexed between McASP0, McBSP1, and GPIO.

AXR0[0]/FSR1/

IPD

I/O/Z

For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 0

GP[105]

DVDD33

AXR0[0] (I/O/Z).

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 3.9.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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