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TNETV2664FIBZWT 数据表(PDF) 120 Page - Texas Instruments |
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TNETV2664FIBZWT 数据表(HTML) 120 Page - Texas Instruments |
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120 / 249 page  TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com (b) Peripherals configuration: see the respective peripheral user’s guide. Special considerations: DDR2 memory controller—the Peripheral Bus Burst Priority Register (PBBPR) should be programmed to ensure good DDR2 throughput and to prevent command starvation (prevention of certain commands from being processed by the DDR2 memory controller). For more details, see the TMS320C642x DSP DDR2 Memory Controller User's Guide (literature number SPRUEM4). A hex value of 0x20 is recommended for the PBBPR PR_OLD_COUNT field to provide a good DSP performance and still allow good utilization by other modules. 120 Device Configurations Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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