TNETV2664FIBZWT datasheet(127/249 Pages) TI1

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TMS320C6424

www.ti.com

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

5.3

Electrical Characteristics Over Recommended Ranges of Supply Voltage and

Operating Temperature (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS (1)

MIN

TYP

MAX

UNIT

High-level output voltage (3.3V I/O except

DVDD33 = MIN, IOH = MAX

2.4

PCI-capable and I2C pins)

VOH

High-level output voltage (3.3V I/O

0.9DVDD33

IOH = -0.5 mA, DVDD33 = 3.3 V

PCI-capable pins)

(2)

Low-level output voltage (3.3V I/O except

DVDD33 = MIN, IOL = MAX

0.4

PCI-capable and I2C pins)

VOL

Low-level output voltage (3.3V I/O

0.1DVDD33

IOH = 1.5 mA, DVDD33 = 3.3 V

PCI-capable pins)

(2)

Low-level output voltage (3.3V I/O I2C pins)

IO = 3 mA

0.4

VI = VSS to DVDD33 with internal pullup resistor

(4)

100

250

μA

Input current [DC] (except I2C and PCI

capable pins)

VI = VSS to DVDD33 with internal pulldown resistor

(4)

–250

–100

–50

μA

Input current [DC] (I2C)

VI = VSS to DVDD33

±10

μA

(3)

0 < VI < DVDD33 = 3.3 V without internal resistor

±50

μA

0 < VI < DVDD33 = 3.3 V with internal pullup resistor

(4)

250

μA

Input current (PCI capable pins) [DC](5)

0 < VI < DVDD33 = 3.3 V with internal pulldown resistor

–250

–50

μA

(4)

CLK_OUT0 /PWM2/GPIO[84] and

-8

VLYNQ_CLOCK/PCICLK/GP[57]

DDR2

–13.4

IOH

High-level output current [DC]

PCI-capable pins

–0.5(2)

All other peripherals

-4

CLK_OUT0 /PWM2/GPIO[84] and

VLYNQ_CLOCK/PCICLK/GP[57]

DDR2

13.4

IOL

Low-level output current [DC]

PCI-capable pins

1.5(2)

All other peripherals

VO = DVDD33 or VSS; internal pull disabled

±50

μA

IOZ

(6)

I/O Off-state output current

VO = DVDD33 or VSS; internal pull enabled

±100

μA

CVDD = 1.2 V, DSP clock = 700 MHz

597

CVDD = 1.2 V, DSP clock = 600 MHz

524

CVDD = 1.2 V, DSP clock = 500 MHz

460

ICDD

Core (CVDD) supply current

(7)

CVDD = 1.2 V, DSP clock = 400 MHz

392

CVDD = 1.05 V, DSP clock = 560 MHz

442

CVDD = 1.05 V, DSP clock = 450 MHz

372

CVDD = 1.05 V, DSP clock = 400 MHz

341

(1)

For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

(2)

These rated numbers are from the PCI Local Bus Specification Revision 2.3. The DC specifications and AC specifications are defined in

Table 4-3 (DC Specifications for 3.3V Signaling) and Table 4-4 (AC Specifications for 3.3V Signaling), respectively.

(3)

II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II

indicates the input leakage current and off-state (Hi-Z) output leakage current.

(4)

Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(5)

PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.

(6)

IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

(7)

Measured under the following conditions: 60% DSP CPU utilization doing typical activity (peripheral configurations, other housekeeping

activities); DDR2 Memory Controller at 50% utilization (135 MHz), 50% writes, 32 bits, 50% bit switching; 2 MHz McBSP0 at 100%

utilization and 50% switching; Timer0 at 100% utilization. At room temperature (25 °C) for typical process ZWT devices. The actual

current draw varies across manufacturing processes and is highly application-dependent. C642x DSP devices are offered in two basic

options: lower-power option and high-performance option. Low-power devices offer lower power consumption across temperature and

voltage when compared with high-performance devices. However, high-performance devices offer higher operating speeds. For more

details on core and I/O activity, as well as information relevant to board power supply design, see the TMS320C642x Power

Consumption Summary Application Report (literature number SPRAAO9).

Device Operating Conditions

127

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