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ST7LITE49K2 数据表(PDF) 161 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 161 Page - STMicroelectronics |
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161 / 245 page  ST7LITE49K2 On-chip peripherals 161/245 The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section : Overrun condition (OVR)). 11.6.5 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 77). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge. Figure 77 shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin and the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. |
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