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ST7LITE49K2 数据表(PDF) 165 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 165 Page - STMicroelectronics |
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165 / 245 page  ST7LITE49K2 On-chip peripherals 165/245 Figure 79. Single master / multiple slave configuration 11.6.7 Low power modes 11.6.8 Interrupts Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). MISO MOSI MOSI MOSI MOSI MOSI MISO MISO MISO MISO SS SS SS SS SS SCK SCK SCK SCK SCK 5V Slave Device Slave Device Slave Device Slave Device Master Device Table 50. Low power mode descriptions Mode Description Wait No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. Halt SPI registers are frozen. In Halt mode, the SPI is inactive. SPI operation resumes when the device is woken up by an interrupt with “exit from Halt mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device. Table 51. Interrupt events Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes No Master Mode Fault Event MODF No Overrun Error OVR |
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