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ST7LITE49K2 数据表(PDF) 167 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 167 Page - STMicroelectronics |
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167 / 245 page  ST7LITE49K2 On-chip peripherals 167/245 Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. The slave must have the same CPOL and CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial clock frequency. These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode. These 2 bits have no effect in slave mode. Table 52. SPI Master mode SCK frequency Serial clock SPR2 SPR1 SPR0 fCPU/4 100 fCPU/8 000 fCPU/16 001 fCPU/32 110 fCPU/64 010 fCPU/128 011 |
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