ST7LITE49K2 datasheet(169/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

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Bit 1 = SSM SS management.

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI SS pin and uses the SSI bit value instead. See Section Slave select

management.

0: Hardware management (SS managed by external pin)

1: Software management (internal SS signal controlled by SSI bit. External SS pin free

for general-purpose I/O)

Bit 0 = SSI SS internal Mode.

This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of

the SS slave select signal when the SSM bit is set.

0: Slave selected

1: Slave deselected

SPI data I/O register (SPIDR)

Reset Value: Undefined

The SPIDR register is used to transmit and receive data on the serial bus. In a master

device, a write to this register will initiate transmission/reception of another byte.

Note:

During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift

buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

Warning:

A write to the SPIDR register places data directly into the

shift register for transmission.

A read to the SPIDR register returns the value located in the buffer and not the content

of the shift register (see Figure 73).

Read / Write

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