ST7LITE49K2 datasheet(166/245 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49K2

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11.6.9

SPI control register (SPICR)

Reset value: 0000 xxxx (0xh)

Bit 7 = SPIE Serial Peripheral interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault

or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)

Bit 6 = SPE Serial Peripheral output enable.

This bit is set and cleared by software. It is also cleared by hardware when, in master

mode, SS =0 (see Section : Master mode fault (MODF)). The SPE bit is cleared by

reset, so the SPI peripheral is not initially connected to the external pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider enable.

This bit is set and cleared by software and is cleared by reset. It is used with the

SPR[1:0] bits to set the baud rate. Refer to Table 52: SPI Master mode SCK Frequency.

0: Divider by 2 enabled

1: Divider by 2 disabled

This bit has no effect in slave mode.

Bit 4 = MSTR Master mode.

This bit is set and cleared by software. It is also cleared by hardware when, in master

mode, SS =0 (see Section : Master mode fault (MODF)).

0: Slave mode

1: Master mode. The function of the SCK pin changes from an input to an output and

the functions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL Clock polarity.

This bit is set and cleared by software. This bit determines the idle state of the serial

Clock. The CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

If CPOL is changed at the communication byte boundaries, the SPI must be disabled

by resetting the SPE bit.

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

Read / Write

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