ST7LITE49K2 datasheet(174/245 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49K2

174/245

11.7.6

Control/status register (ADCCSR)

Reset value: 0000 0000 (00h)

Bit 7 = EOC End of conversion bit

This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH

0: Conversion is not complete

1: Conversion complete

Bit 6 = SPEED ADC clock selection bit

This bit is set and cleared by software. It is used together with the SLOW bit to

configure the ADC clock speed. Refer to the table in the SLOW bit description

(ADCDRL register).

Bit 5 = ADON A/D converter ON bit

This bit is set and cleared by software.

0: A/D converter is switched off

1: A/D converter is switched on

Bit 4 = Reserved, must be kept cleared.

Bits 3:0 = CH[3:0] Channel selection

These bits select the analog input to convert. They are set and cleared by software.

EOC

SPEED

ADON

CH3

CH2

CH1

CH0

Read only

Read/write

Table 55.

Channel selection using CH[3:0]

Channel pin(1)

The number of channels is device dependent. Refer to the device pinout description.

CH3

CH2

CH1

CH0

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

ST7LITE49K2 数据表(PDF) 174 Page - STMicroelectronics

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