ST7LITE49K2 datasheet(175/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

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Data register high (ADCDRH)

Reset value: xxxx xxxx (xxh)

Bits 7:0 = D[9:2] MSB of Analog Converted Value

ADC control/data register low (ADCDRL)

Reset value: 0000 00xx (0xh)

Bits 7:5 = Reserved. Forced by hardware to 0.

Bit 4 = AMPCAL Amplifier calibration bit

This bit is set and cleared by software. It is advised to use this bit to calibrate the ADC

when amplifier is ON. Setting this bit internally connects amplifier input to 0V. Hence,

corresponding ADC output can be used in software to eliminate amplifier-offset error.

0: Calibration off

1: Calibration on (The input voltage of the amplifier is set to 0V)

Bit 3 = SLOW Slow mode bit

This bit is set and cleared by software. It is used together with the SPEED bit in the

ADCCSR register to configure the ADC clock speed as shown on the table below.

Bit 2 = AMPSEL Amplifier selection bit

This bit is set and cleared by software.

0: Amplifier is not selected

1: Amplifier is selected

Note:

When AMPSEL=1 it is mandatory that fADC be less than or equal to 2 MHz.

Bits 1:0 = D[1:0] LSB of analog converted value

Read only

AMPCAL

SLOW

AMPSEL

Read/write

Table 56.

Configuring the ADC clock speed

fADC

(1)

The maximum allowed value of fADC is 4 MHz (see Section 13.11 on page 226)

SLOW

SPEED

fCPU/2

fCPU

fCPU/4

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