ST7LITE49K2 datasheet(207/245 Pages) STMICROELECTRONICS

207 / 245 page

ST7LITE49K2

Electrical characteristics

207/245

Figure 97.

SPI master timing diagram

Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave

mode) has its alternate function capability released. In this case, the pin status depends of the I/O port

configuration.

13.6

Clock and timing characteristics

Subject to general operating conditions for VDD, fOSC, and TA.

SS INPUT

CPHA = 0

MOSI OUTPUT

MISO INPUT

CPHA = 0

CPHA = 1

tc(SCK)

tw(SCKH)

tw(SCKL)

th(MI)

tsu(MI)

MSB IN

MSB OUT

BIT6 IN

BIT6 OUT

LSB OUT

LSB IN

See note 2

Seenote2

CPOL = 0

CPOL = 1

CPOL = 0

CPOL = 1

tr(SCK)

tf(SCK)

th(MO)

tv(MO)

Table 83.

General timings

Symbol

Parameter(1)

Guaranteed by Design. Not tested in production.

Conditions

Min

Typ(2)

Data based on typical application software.

Max

Unit

tc(INST)

Instruction cycle time

fCPU = 8 MHz

tCPU

250

375

1500

tv(IT)

Interrupt reaction time(3)

tv(IT) = Δtc(INST) + 10

Time measured between interrupt event and interrupt vector fetch.

Δtc(INST) is the number of tCPU cycles

needed to finish the current instruction execution.

fCPU = 8 MHz

tCPU

1.25

2.75

μs

ST7LITE49K2 数据表(PDF) 207 Page - STMicroelectronics

ST7LITE49K2 数据表(HTML) 207 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载