LSM6DSV datasheet(56/187 Pages) STMICROELECTRONICS

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9.4

FIFO_CTRL1 (07h)

FIFO control register 1 (R/W)

Table 29. FIFO_CTRL1 register

WTM_7

WTM_6

WTM_5

WTM_4

WTM_3

WTM_2

WTM_1

WTM_0

Table 30. FIFO_CTRL1 register description

WTM_[7:0]

FIFO watermark threshold: 1 LSB = TAG (1 byte) + 1 sensor (6 bytes) written in FIFO.

Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.

9.5

FIFO_CTRL2 (08h)

FIFO control register 2 (R/W)

Table 31. FIFO_CTRL2 register

STOP_ON

_WTM

FIFO_COMPR

_RT_EN

0(1)

ODR_CHG

_EN

0(1)

UNCOMPR

_RATE_1

UNCOMPR

_RATE_0

XL_DualC_BATCH

_FROM_FSM

1. This bit must be set to 0 for the correct operation of the device.

Table 32. FIFO_CTRL2 register description

STOP_ON_WTM

Sensing chain FIFO stop values memorization at threshold level. Default value: 0

(0: FIFO depth is not limited;

1: FIFO depth is limited to threshold level, defined in FIFO_CTRL1 (07h))

FIFO_COMPR_RT_EN(1)

Enables/disables compression algorithm runtime. Default value: 0

(0: FIFO compression algorithm disabled;

1: FIFO compression algorithm enabled)

ODR_CHG_EN

Enables ODR CHANGE virtual sensor to be batched in FIFO. Default value: 0

(0: ODR CHANGE virtual sensor not batched in FIFO;

1: ODR CHANGE virtual sensor batched in FIFO)

UNCOMPR_RATE_[1:0]

This field configures the compression algorithm to write uncompressed data at each rate.

(0: uncompressed data writing is not forced (default);

1: uncompressed data every 8 batch data rate;

2: uncompressed data every 16 batch data rate;

3: uncompressed data every 32 batch data rate)

XL_DualC_BATCH_FROM_FSM

When dual-channel mode is enabled, this bit enables FSM-triggered batching in FIFO of

accelerometer channel 2. Default value: 0

(0: disabled; 1: enabled)

1. This bit is activated if the FIFO_COMPR_EN bit of EMB_FUNC_EN_B (05h) is set to 1.

LSM6DSV

FIFO_CTRL1 (07h)

DS13476 - Rev 2

page 56/187

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