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LSM6DSV 数据表(PDF) 60 Page - STMicroelectronics |
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LSM6DSV 数据表(HTML) 60 Page - STMicroelectronics |
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60 / 187 page  9.10 INT1_CTRL (0Dh) INT1 pin control register (R/W) Each bit in this register enables a signal to be carried over INT1 when the MIPI I3C® dynamic address is not assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI (in-band interrupt) when the MIPI I3C® interface is used. The output of the pin is the OR combination of the signals selected here and in MD1_CFG (5Eh). Table 41. INT1_CTRL register 0(1) INT1_ CNT_BDR INT1_ FIFO_FULL INT1_ FIFO_OVR INT1_ FIFO_TH 0(1) INT1_ DRDY_G INT1_ DRDY_XL 1. This bit must be set to 0 for the correct operation of the device. Table 42. INT1_CTRL register description INT1_CNT_BDR Enables COUNTER_BDR_IA interrupt on INT1 pin. Default value: 0 INT1_FIFO_FULL Enables FIFO full flag interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3C ® interface is used. Default value: 0 INT1_FIFO_OVR Enables FIFO overrun interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3C® interface is used. Default value: 0 INT1_FIFO_TH Enables FIFO threshold interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3C® interface is used. Default value: 0 INT1_DRDY_G Enables gyroscope data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3C® interface is used. Default value: 0 INT1_DRDY_XL Enables accelerometer data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3C® interface is used. Default value: 0 LSM6DSV INT1_CTRL (0Dh) DS13476 - Rev 2 page 60/187 |
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