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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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LSM6DSV 数据表(PDF) 64 Page - STMicroelectronics |
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LSM6DSV 数据表(HTML) 64 Page - STMicroelectronics |
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64 / 187 page  9.15 CTRL3 (12h) Control register 3 (R/W) Table 52. CTRL3 register BOOT BDU 0(1) 0(1) 0(1) IF_INC 0(1) SW_RESET 1. This bit must be set to 0 for the correct operation of the device. Table 53. CTRL3 register description BOOT Reboots memory content (the accelerometer must not be in power-down mode). This bit is automatically cleared. Default value: 0 (0: normal mode; 1: reboot memory content) This bit is automatically cleared. BDU Block data update. Default value: 1 (0: continuous update; 1: output registers are not updated until LSB and MSB have been read) IF_INC Register address automatically incremented during a multiple byte access with a serial interface (I²C, MIPI I3C, or SPI). Default value: 1 (0: disabled; 1: enabled) SW_RESET Software reset, resets all control registers to their default value. This bit is automatically cleared. Default value: 0 (0: normal mode; 1: reset device) LSM6DSV CTRL3 (12h) DS13476 - Rev 2 page 64/187 |
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