LSM6DSV datasheet(93/187 Pages) STMICROELECTRONICS

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9.57

TAP_DUR (5Ah)

Tap recognition function setting register (R/W)

Table 155. TAP_DUR register

DUR_3

DUR_2

DUR_1

DUR_0

QUIET_1

QUIET_0

SHOCK_1

SHOCK_0

Table 156. TAP_DUR register description

DUR_[3:0]

Duration of maximum time gap for double-tap recognition. Default: 0000

When double-tap recognition is enabled, this register expresses the maximum time between two consecutive

detected taps to determine a double-tap event. The default value of these bits is 0000b which corresponds to

16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.

QUIET_[1:0]

Expected quiet time after a tap detection. Default value: 00

Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The

default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET_[1:0] bits are set to a

different value, 1LSB corresponds to 4/ODR_XL time.

SHOCK_[1:0]

Maximum duration of overthreshold event. Default value: 00

Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event.

The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK_[1:0] bits are set to

a different value, 1LSB corresponds to 8/ODR_XL time.

9.58

WAKE_UP_THS (5Bh)

Single/double-tap selection and wake-up configuration (R/W)

Table 157. WAKE_UP_THS register

SINGLE_

DOUBLE_TAP

USR_OFF

_ON_WU

WK_THS_5

WK_THS_4

WK_THS_3

WK_THS_2

WK_THS_1

WK_THS_0

Table 158. WAKE_UP_THS register description

SINGLE_DOUBLE_TAP

Enables single/double-tap event. Default value: 0

(0: only single-tap event enabled;

1: both single and double-tap events enabled)

USR_OFF_ON_WU

Drives the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the

wake-up and the activity/inactivity functions. Refer to Figure 30. Default value: 0

WK_THS_[5:0]

Wake-up threshold. The resolution of the threshold depends on the value of

WU_INACT_THS_W_[2:0] in the INACTIVITY_DUR (54h) register. Default value: 000000

LSM6DSV

TAP_DUR (5Ah)

DS13476 - Rev 2

page 93/187

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