LSM6DSV datasheet(89/187 Pages) STMICROELECTRONICS

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9.51

INACTIVITY_DUR (54h)

Activity/inactivity configuration register (R/W)

Table 141. INACTIVITY_DUR register

SLEEP_STATUS

_ON_INT

WU_INACT_

THS_W_2

WU_INACT_

THS_W_1

WU_INACT_

THS_W_0

XL_INACT

_ODR_1

XL_INACT

_ODR_0

INACT

_DUR_1

INACT

_DUR_0

Table 142. INACTIVITY_DUR register description

SLEEP_STATUS_ON_INT

Activity/inactivity interrupt mode configuration.

If the INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bit is enabled, drives the sleep status

or sleep change on the INT pin. Default value: 0

(0: sleep change notification on INT pin;

1: sleep status reported on INT pin)

WU_INACT_THS_W_[2:0]

Weight of 1 LSB of wake-up (WU_THS) and activity/inactivity (INACT_THS) threshold.

(000: 7.8125 mg/LSB (default);

001: 15.625 mg/LSB;

010: 31.25 mg/LSB;

011: 62.5 mg/LSB;

100: 125 mg/LSB;

101 - 110 - 111: 250 mg/LSB)

XL_INACT_ODR_[1:0]

Selects the ODR_XL target during inactivity.

(00: 1.875 Hz;

01: 15 Hz (default);

10: 30 Hz;

11: 60 Hz)

INACT_DUR_[1:0]

Duration in the transition from stationary to motion (from inactivity to activity).

(00: transition to motion (activity) immediately at first overthreshold event (default);

01: transition to motion (activity) after two consecutive overthreshold events;

10: transition to motion (activity) after three consecutive overthreshold events;

11: transition to motion (activity) after four consecutive overthreshold events)

9.52

INACTIVITY_THS (55h)

Activity/inactivity threshold setting register (R/W)

Table 143. INACTIVITY_THS register

0(1)

INACT_

THS_5

INACT_

THS_4

INACT_

THS_3

INACT_

THS_2

INACT_

THS_1

INACT_

THS_0

1. This bit must be set to 0 for the correct operation of the device.

Table 144. INACTIVITY_THS register description

INACT_THS_[5:0]

Activity/inactivity threshold. The resolution of the threshold depends on the value of

WU_INACT_THS_W_[2:0] in the INACTIVITY_DUR (54h) register. Default value: 000000

LSM6DSV

INACTIVITY_DUR (54h)

DS13476 - Rev 2

page 89/187

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