DSP56303 datasheet(146/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

7-14

Freescale Semiconductor

Enhanced Synchronous Serial Interface (ESSI)

21–19

WL[2–0]

Word Length Control

Select the length of the data words transferred via the ESSI. Word lengths of

8-, 12-, 16-, 24-, or 32-bits can be selected. The ESSI data path programming

model in Figure 7-12 and Figure 7-13 shows additional information on how to

select different lengths for data words. The ESSI data registers are 24 bits

long. The ESSI transmits 32-bit words in one of two ways:

• By duplicating the last bit 8 times when WL[2–0] = 100

• By duplicating the first bit 8 times when WL[2–0] = 101.

Note:

When WL[2–0] = 100, the ESSI is designed to duplicate the last bit of

the 24-bit transmission eight times to fill the 32-bit shifter. Instead,

after the 24-bit word is shifted correctly, eight zeros (0s) are shifted.

ESSI Word Length Selection

WL2

WL1

WL0

Number of Bits/Word

(valid data in the first 24

bits)

(valid data in the last 24

bits)

Reserved

Note:

When the ESSI transmits data in On-Demand mode (that is, MOD = 1

in the CRB and DC[4–0]=00000 in the CRA) with WL[2–0] = 100, the

transmission does not work properly. To ensure correct operation, do

not use On-Demand mode with the WL[2–0] = 100 32-bit word length

mode.

ALC

Alignment Control

The ESSI handles 24-bit fractional data. Shorter data words are left-aligned to

the MSB, bit 23. For applications that use 16-bit fractional data, shorter data

words are left-aligned to bit 15. The ALC bit supports shorter data words. If

ALC is set, received words are left-aligned to bit 15 in the receive shift register.

Transmitted words must be left-aligned to bit 15 in the transmit shift register. If

the ALC bit is cleared, received words are left-aligned to bit 23 in the receive

shift register. Transmitted words must be left-aligned to bit 23 in the transmit

shift register.

Note:

If the ALC bit is set, only 8-, 12-, or 16-bit words are used. The use of

24- or 32-bit words leads to unpredictable results.

Reserved. Write to 0 for future compatibility.

Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

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