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AM79C971VCW 数据表(PDF) 111 Page - Advanced Micro Devices |
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AM79C971VCW 数据表(HTML) 111 Page - Advanced Micro Devices |
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111 / 265 page  Am79C971 111 6-0 RES Reserved locations. Read as ze- ro; write operations have no ef- fect. PCI Revision ID Register Offset 08h The PCI Revision ID register is an 8-bit register that specifies the Am79C971 controller revision number. The value of this register is 2Xh, with the lower four bits being silicon-revision dependent. The initial revision value will be 21h. The PCI Revision ID register is located at offset 08h in the PCI Configuration Space. It is read only. PCI Programming Interface Register Offset 09h The PCI Programming Interface register is an 8-bit reg- ister that identifies the programming interface of Am79C971 controller. PCI does not define any specific register-level programming interfaces for network de- vices. The value of this register is 00h. The PCI Programming Interface register is located at offset 09h in the PCI Configuration Space. It is read only. PCI Sub-Class Register Offset 0Ah The PCI Sub-Class register is an 8-bit register that identifies specifically the function of the Am79C971 controller. The value of this register is 00h which iden- tifies the Am79C971 device as an Ethernet controller. The PCI Sub-Class register is located at offset 0Ah in the PCI Configuration Space. It is read only. PCI Base-Class Register Offset 0Bh The PCI Base-Class register is an 8-bit register that broadly classifies the function of the Am79C971 con- troller. The value of this register is 02h which classifies the Am79C971 device as a network controller. The PCI Base-Class register is located at offset 0Bh in the PCI Configuration Space. It is read only. PCI Latency Timer Register Offset 0Dh The PCI Latency Timer register is an 8-bit register that specifies the minimum guaranteed time the Am79C971 controller will control the bus once it starts its bus mas- tership period. The time is measured in clock cycles. Every time the Am79C971 controller asserts FRAME at the beginning of a bus mastership period, it will copy the value of the PCI Latency Timer register into a counter and start counting down. The counter will freeze at 0. When the system arbiter removes GNT while the counter is non-zero, the Am79C971 controller will continue with its data transfers. It will only release the bus when the counter has reached 0. The PCI Latency Timer is only significant in burst trans- actions, where FRAME stays asserted until the last data phase. In a non-burst transaction, FRAME is only asserted during the address phase. The internal la- tency counter will be cleared and suspended while FRAME is deasserted. All eight bits of the PCI Latency Timer register are pro- grammable. The host should read the Am79C971 PCI MIN_GNT and PCI MAX_LAT registers to determine the latency requirements for the device and then initial- ize the Latency Timer register with an appropriate value. The PCI Latency Timer register is located at offset 0Dh in the PCI Configuration Space. It is read and written by the host. The PCI Latency Timer register is cleared by H_RESET and is not effected by S_RESET or by set- ting the STOP bit. PCI Header Type Register Offset 0Eh The PCI Header Type register is an 8-bit register that describes the format of the PCI Configuration Space lo- cations 10h to 3Ch and that identifies a device to be single or multi-function. The PCI Header Type register is located at address 0Eh in the PCI Configuration Space. It is read only. Bit Name Description 7 FUNCT Single-function/multi-function de- vice. Read as zero; write opera- tions have no effect. The Am79C971 controller is a single function device. 6-0 LAYOUT PCI configuration space layout. Read as zeros; write operations have no effect. The layout of the PCI configuration space loca- tions 10h to 3Ch is as shown in the table at the beginning of this section. PCI I/O Base Address Register Offset 10h The PCI I/O Base Address register is a 32-bit register that determines the location of the Am79C971 I/O re- sources in all of I/O space. It is located at offset 10h in the PCI Configuration Space. Bit Name Description 31-5 IOBASE I/O base address most significant 27 bits. These bits are written by the host to specify the location of the Am79C971 I/O resources in |
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