AM79C971VCW datasheet(115/265 Pages) AMD

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Am79C971

115

read access will yield undefined

values.

Read/Write accessible always.

RAP is cleared by H_RESET or

S_RESET and is unaffected by

setting the STOP bit.

Control and Status Registers

The CSR space is accessible by performing accesses

to the RDP (Register Data Port). The particular CSR

that is read or written during an RDP access will de-

pend upon the current setting of the RAP. RAP serves

as a pointer into the CSR space.

CSR0: Am79C971 Controller Status and Control

Certain bits in CSR0 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR0 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

ERR

Error is set by the OR of BABL,

CERR, MISS, and MERR. ERR

remains set as long as any of the

error flags are true.

Read accessible always. ERR is

read only. Write operations are

ignored.

BABL

Babble is a transmitter time-out

error.

BABL

set

the

Am79C971 controller when the

transmitter has been on the chan-

nel longer than the time required

to send the maximum length

frame. BABL will be set if 1519

bytes or greater are transmitted.

When BABL is set, INTA is as-

serted if IENA is 1 and the mask

bit BABLM (CSR3, bit 14) is 0.

BABL assertion will set the ERR

bit, regardless of the settings of

IENA and BABLM.

Read/Write accessible always.

BABL is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

BABL

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

CERR

Collision Error is set by the

Am79C971 controller when the

device operates in half-duplex

mode and the collision inputs to

the AUI or to the GPSI port failed

to activate within 20 network bit

times after the chip terminated

transmission (SQE Test). This

feature is a transceiver test fea-

ture. CERR reporting is disabled

when the AUI or the GPSI port is

active and the Am79C971 con-

troller

operates

full-duplex

mode.

When the 10BASE-T port is se-

lected, for both half-duplex and

full-duplex operation, CERR will

be set after a transmission if the

T-MAU is in Link Fail state.

When the MII port is selected,

CERR is only reported when the

external PHY is operating as a

10BASE-T PHY and if the exter-

nal T-MAU is in Link Fail state.

CERR assertion will not result in

an interrupt being generated.

CERR assertion will set the ERR

bit.

Read/Write accessible always.

CERR is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

CERR

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

MISS

Missed Frame is set by the

Am79C971 controller when it has

lost an incoming receive frame

resulting from a Receive Descrip-

tor not being available. This bit is

the only immediate indication that

receive data has been lost since

there is no current receive de-

scriptor.

The

Missed

Frame

Counter (CSR112) also incre-

ments each time a receive frame

is missed.

When MISS is set, INTA is as-

serted if IENA is 1 and the mask

bit MISSM (CSR3, bit 12) is 0.

MISS assertion will set the ERR

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