AM79C971VCW datasheet(116/265 Pages) AMD

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116

Am79C971

bit, regardless of the settings of

IENA and MISSM.

Read/Write accessible always.

MISS is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MISS

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

MERR

Memory Error is set by the

Am79C971 controller when it re-

quests the use of the system in-

terface bus by asserting REQ

and has not received GNT asser-

tion after a programmable length

of time. The length of time in mi-

croseconds before MERR is as-

serted will depend upon the

setting of the Bus Timeout Regis-

ter (CSR100). The default setting

of CSR100 will give a MERR after

153.6

µs of bus latency.

When MERR is set, INTA is as-

serted if IENA is 1 and the mask

bit MERRM (CSR3, bit 11) is 0.

MERR assertion will set the ERR

bit, regardless of the settings of

IENA and MERRM.

Read/Write accessible always.

MERR is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MERR

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

RINT

Receive Interrupt is set by the

Am79C971 controller after the

last descriptor of a receive frame

has been updated by writing a 0

to the OWNership bit. RINT may

also be set when the first descrip-

tor of a receive frame has been

updated by writing a 0 to the

OWNership bit if the LAPPEN bit

of CSR3 has been set to a 1.

When RINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

RINTM (CSR3, bit 10) is 0.

Read/Write accessible always.

RINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

RINT

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

TINT

Transmit Interrupt is set by the

Am79C971 controller after the

OWN bit in the last descriptor of a

transmit frame has been cleared

to indicate the frame has been

sent or an error occurred in the

transmission.

When TINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

TINTM (CSR3, bit 9) is 0.

TINT will not be set if TINTOKD

(CSR5, bit 15) is set to 1 and the

transmission was successful.

Read/Write accessible always.

TINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

TINT

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

IDON

Initialization Done is set by the

Am79C971 controller after the

initialization sequence has com-

pleted. When IDON is set, the

Am79C971 controller has read

the initialization block from mem-

ory.

When IDON is set, INTA is as-

serted if IENA is 1 and the mask

bit IDONM (CSR3, bit 8) is 0.

Read/Write accessible always.

IDON is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

IDON

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

INTR

Interrupt Flag indicates that one

or more following interrupt caus-

ing

conditions

has

occurred:

BABL,

EXDINT,

IDON,

JAB,

MERR, MISS, MFCO, RCVCCO,

RINT, SINT, SLPINT, TINT, TX-

STRT, UINT, STINT, MREINT,

MCCINT, MCCIINT, MIIPDTINT,

MAPINT

and

the

associated

mask

enable

bit

pro-

grammed to allow the event to

cause an interrupt. If IENA is set

to 1 and INTR is set, INTA will be

active. When INTR is set by SINT

or SLPINT, INTA will be active in-

dependent of the state of IENA.

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