AM79C971VCW datasheet(122/265 Pages) AMD

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122

Am79C971

ASTRP_RCV Auto Strip Receive. When set,

ASTRP_RCV enables the auto-

matic pad stripping feature. The

pad and FCS fields will be

stripped from receive frames and

not placed in the FIFO.

Read/Write accessible always.

ASTRP_RCV

cleared

H_RESET or S_RESET and is

unaffected by the STOP bit.

MFCO

Missed Frame Counter Overflow

is set by the Am79C971 control-

ler

when the

Missed

Frame

Counter (CSR112 and CSR114)

has wrapped around.

When MFCO is set, INTA is as-

serted if IENA is 1 and the mask

bit MFCOM is 0.

Read/Write accessible always.

MFCO is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MFCO

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

MFCOM

Missed Frame Counter Overflow

Mask. If MFCOM is set, the

MFCO bit will be masked and un-

able to set the INTR bit.

Read/Write accessible always.

MFCOM is set to 1 by H_RESET

or S_RESET and is not affected

by the STOP bit.

UINTCMD

User

Interrupt

Command.

UINTCMD can be used by the

host to generate an interrupt un-

related to any network activity.

When UINTCMD is set, INTA is

asserted if IENA is set to 1.

UINTCMD will be cleared inter-

nally after the Am79C971 control-

ler has set UINT to 1.

Read/Write accessible always.

UINTCMD

cleared

H_RESET or S_RESET or by

setting the STOP bit.

UINT

User Interrupt. UINT is set by the

Am79C971 controller after the

host has issued a user interrupt

command by setting UINTCMD

(CSR4, bit 7) to 1.

Read/Write accessible always.

UINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

UINT

cleared

H_RESET or S_RESET or by

setting the STOP bit.

RCVCCO

Receive Collision Counter Over-

flow is set by the Am79C971 con-

troller when the Receive Collision

Counter (CSR114 and CSR115)

has wrapped around.

When RCVCCO is set, INTA is

asserted if IENA is 1 and the

mask bit RCVCCOM is 0.

Read/Write accessible always.

RCVCCO is cleared by the host

by writing a 1. Writing a 0 has no

effect. RCVCCO is cleared by

H_RESET, S_RESET, or by set-

ting the STOP bit.

RCVCCOM Receive Collision Counter Over-

flow Mask. If RCVCCOM is set,

the RCVCCO bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

RCVCCOM

set

H_RESET or S_RESET and is

not affected by the STOP bit.

TXSTRT

Transmit Start status is set by the

Am79C971 controller whenever it

begins transmission of a frame.

When TXSTRT is set, INTA is as-

serted if IENA is 1 and the mask

bit TXSTRTM is 0.

Read/Write accessible always.

TXSTRT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

TXSTRT

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

TXSTRTM

Transmit

Start

Mask.

TX-

STRTM is set, the TXSTRT bit

will be masked and unable to set

the INTR bit.

Read/Write accessible always.

TXSTRTM

set

H_RESET or S_RESET and is

not affected by the STOP bit.

AM79C971VCW 数据表(PDF) 122 Page - Advanced Micro Devices

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AM79C971VCW 数据表(PDF) 122 Page - Advanced Micro Devices

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