AM79C971VCW datasheet(126/265 Pages) AMD

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126

Am79C971

CSR7: Extended Control and Interrupt 2

Certain bits in CSR7 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR7 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

FASTSPNDE

Fast Suspend Enable. When

FASTSPNDE is set to 1, the

Am79C971 controller performs a

fast

suspend

whenever

the

SPND bit is set.

When a fast suspend is request-

ed, the Am79C971 controller per-

forms a quick entry into the

suspend mode. At the time the

SPND bit is set, the Am79C971

controller will complete the DMA

process of any transmit and/or re-

ceive packet that had already be-

gun DMA activity. In addition, any

transmit packet that had started

transmission will be fully transmit-

ted and any receive packet that

had begun reception will be fully

received. However, no additional

packets will be transmitted or re-

ceived and no additional transmit

or receive DMA activity will begin.

Hence, the Am79C971 controller

may enter the suspend mode

with

transmit

and/or

receive

packets still in the FIFOs or exter-

nal SRAM.

When FASTSPNDE is 0 and the

SPND bit is set, the Am79C971

controller may take longer before

entering the suspend mode. At

the time the SPND bit is set, the

Am79C971 controller will com-

plete the DMA process of a trans-

mit packet if it had already begun

and the Am79C971 controller will

completely

receive

packet if it had already begun.

Additionally, all transmit packets

stored in the transmit FIFOs and

the transmit buffer area in the ex-

ternal SRAM (if one is present)

will be transmitted and all receive

packets stored in the receive

FIFOs, and the receive buffer

area in the external SRAM (if one

is present) will be transferred into

system memory. Since the FIFO

and external SRAM contents are

flushed, it may take much longer

before the Am79C971 controller

enters the suspend mode. The

amount of time that it takes de-

pends on many factors including

the size of the external SRAM,

bus latency, and network traffic

level.

When a write to CSR5 is per-

formed with bit 0 (SPND) set to 1,

the value that is simultaneously

written to FASTSPNDE is used to

determine which approach

used to enter suspend mode.

Read/Write accessible always.

FASTSPNDE

cleared

H_RESET, S_RESET or by set-

ting the STOP bit.

RXFRTG

Receive Frame Tag. When Re-

ceive Frame Tag is set to 1, a tag

word is put into the receive de-

scriptor supplied by the EADI.

See the section Receive Frame

Tagging for details. This bit is

valid only when the EADISEL

(BCR2, bit 3) is set to 1.

Read/Write accessible always.

RXFRTG

cleared

H_RESET. RXFRTG is unaffect-

ed by S_RESET or by setting the

STOP bit.

RDMD

Receive

Demand,

when

set,

causes the Buffer Management

Unit to access the Receive De-

scriptor Ring without waiting for

the receive poll-time counter to

elapse. If RXON is not enabled,

RDMD has no meaning and no

receive Descriptor Ring access

will occur.

RDMD is required to be set if the

RXDPOLL bit in CSR7 is set. Set-

ting RDMD while RXDPOLL = 0

merely hastens the Am79C971

controller’s response to a receive

Descriptor Ring Entry.

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