AM79C971VCW datasheet(128/265 Pages) AMD

128 / 265 page

128

Am79C971

When MAPINT is set to 1, INTA is

asserted if the enable bit MAP-

INTE is set to 1.

Read/Write accessible always.

MAPINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MAPINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MAPINTE

MII Auto-Poll Interrupt Enable. If

MAPINTE is set, the MAPINT bit

will be able to set the INTR bit.

Read/Write accessible always.

MAPINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP bit

MCCINT

MII

Management

Command

Complete Interrupt. The MII Man-

agement Command Complete In-

terrupt is set by the Am79C971

controller when a read or write

operation to the MII Data Port

(BCR34) is complete.

When MCCINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

Read/Write accessible always.

MCCINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MCCINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MCCINTE

MII

Management

Command

Complete Interrupt Enable. If

MCCINTE is set to 1, the MC-

CINT bit will be able to set the

INTR bit when the host reads or

writes to the MII Data Port

(BCR34) only. Internal MII Man-

agement Commands will not gen-

erate an interrupt. For instance

Auto-Poll state machine generat-

ed MII management frames will

not generate an interrupt upon

completion unless there is a com-

pare error which get reported

through the MAPINT (CSR7, bit

6) interrupt or the MCCIINTE is

set to 1.

Read/Write accessible always.

MCCINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MCCIINT

MII

Management

Command

Complete Internal Interrupt. The

MII

Management

Command

Complete Interrupt is set by the

Am79C971 controller when a

read or write operation on the MII

management port is complete

from an internal operation. Exam-

ples of internal operations are

Auto-Poll or MII Management

Port generated MII management

frames. These are normally hid-

den to the host.

When MCCIINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

Read/Write accessible always.

MCCIINT is cleared by the host

by writing a 1. Writing a 0 has no

effect. MCCIINT is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MCCIINTE

MII

Management

Command

Complete Internal Interrupt En-

able. If MCCIINTE is set to 1, the

MCCIINT bit will be able to set

the INTR bit when the internal

state

machines

generate

MII

management

frames.

For

in-

stance, when MCCIINTE is set to

1 and the Auto-Poll state ma-

chine generates a MII manage-

ment frame, the MCCIINT will set

the INTR bit upon completion of

the MII management frame re-

gardless of the comparison out-

come.

Read/Write accessible always.

MCCIINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

AM79C971VCW 数据表(PDF) 128 Page - Advanced Micro Devices

AM79C971VCW 数据表(HTML) 128 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AM79C971VCW 数据表(PDF) 128 Page - Advanced Micro Devices

AM79C971VCW 数据表(HTML) 128 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载