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数据搜索系统，热门电子元器件搜索 |
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AM79C971VCW 数据表(PDF) 129 Page - Advanced Micro Devices |
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AM79C971VCW 数据表(HTML) 129 Page - Advanced Micro Devices |
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129 / 265 page  Am79C971 129 1 MIIPDTINT MII PHY Detect Transition Inter- rupt. The MII PHY Detect Transi- tion Interrupt is set by the Am79C971 controller whenever the MIIPD bit (BCR32, bit 14) transitions from 0 to 1 or vice ver- sa. Read/Write accessible always. MIIPDTINT is cleared by the host by writing a 1. Writing a 0 has no effect. MIIPDTINT is cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. 0 MIIPDTINTE MII PHY Detect Transition Inter- rupt Enable. If MIIPDTINTE is set to 1, the MIIPDTINT bit will be able to set the INTR bit. Read/Write accessible always. MIIPDTINTE is set to 0 by H_RESET and is not affected by S_RESET or setting the STOP bit. CSR8: Logical Address Filter 0 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 LADRF[15:0] Logical Address Filter, LADRF- [15:0]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSR0 has been set or a di- rect register write has been per- formed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR9: Logical Address Filter 1 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 LADRF[31:16] Logical Address Filter, LADRF- [31:16]. The content of this regis- ter is undefined until loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR10: Logical Address Filter 2 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 LADRF[47:32] Logical Address Filter, LADRF[47:32]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR11: Logical Address Filter 3 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 LADRF[63:48] Logical Address Filter, LADRF[63:48]. The content of this register is undefined until loaded from the initialization block after the INIT bit in CSR0 has been set or a direct register write has been performed on this register. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR12: Physical Address Register 0 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. |
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