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数据搜索系统，热门电子元器件搜索 |
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AM79C971VCW 数据表(PDF) 133 Page - Advanced Micro Devices |
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AM79C971VCW 数据表(HTML) 133 Page - Advanced Micro Devices |
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133 / 265 page  Am79C971 133 Read/Write accessible only when either the STOP or the SPND bit is set. LOOP is cleared by H_RESET or S_RESET and is unaffected by STOP. 1 DTX Disable Transmit results in Am79C971 controller not access- ing the Transmit Descriptor Ring and, therefore, no transmissions are attempted. DTX = 0, will set TXON bit (CSR0 bit 4) if STRT (CSR0 bit 1) is asserted. Read/Write accessible only when either the STOP or the SPND bit is set. 0 DRX Disable Receiver results in the Am79C971 controller not access- ing the Receive Descriptor Ring and, therefore, all receive frame data are ignored. DRX = 0, will set RXON bit (CSR0 bit 5) if STRT (CSR0 bit 1) is asserted. Read/Write accessible only when either the STOP or the SPND bit is set. CSR16: Initialization Block Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 IADRL This register is an alias of CSR1. Read/Write accessible only when either the STOP or the SPND bit is set. CSR17: Initialization Block Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 IADRH This register is an alias of CSR2. Read/Write accessible only when either the STOP or the SPND bit is set. CSR18: Current Receive Buffer Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CRBAL Contains the lower 16 bits of the current receive buffer address at which the Am79C971 controller will store incoming frame data. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR19: Current Receive Buffer Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CRBAU Contains the upper 16 bits of the current receive buffer address at which the Am79C971 controller will store incoming frame data. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR20: Current Transmit Buffer Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CXBAL Contains the lower 16 bits of the current transmit buffer address from which the Am79C971 con- troller is transmitting. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR21: Current Transmit Buffer Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. |
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