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数据搜索系统，热门电子元器件搜索 |
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AM79C971VCW 数据表(PDF) 134 Page - Advanced Micro Devices |
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AM79C971VCW 数据表(HTML) 134 Page - Advanced Micro Devices |
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134 / 265 page  134 Am79C971 15-0 CXBAU Contains the upper 16 bits of the current transmit buffer address from which the Am79C971 con- troller is transmitting. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR22: Next Receive Buffer Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NRBAL Contains the lower 16 bits of the next receive buffer address to which the Am79C971 controller will store incoming frame data. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR23: Next Receive Buffer Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NRBAU Contains the upper 16 bits of the next receive buffer address to which the Am79C971 controller will store incoming frame data. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR24: Base Address of Receive Ring Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 BADRL Contains the lower 16 bits of the base address of the Receive Ring. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR25: Base Address of Receive Ring Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 BADRU Contains the upper 16 bits of the base address of the Receive Ring. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR26: Next Receive Descriptor Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NRDAL Contains the lower 16 bits of the next receive descriptor address pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR27: Next Receive Descriptor Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NRDAU Contains the upper 16 bits of the next receive descriptor address pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR28: Current Receive Descriptor Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. |
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