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AM79C971VCW 数据表(PDF) 137 Page - Advanced Micro Devices |
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AM79C971VCW 数据表(HTML) 137 Page - Advanced Micro Devices |
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137 / 265 page  Am79C971 137 CSR42: Current Transmit Byte Count Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-12 RES Reserved locations. Read and written as zeros. 11-0 CXBC Current Transmit Byte Count. This field is a copy of the BCNT field of TMD1 of the current trans- mit descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR43: Current Transmit Status Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CXST Current Transmit Status. This field is a copy of bits 31-16 of TMD1 of the current transmit de- scriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR44: Next Receive Byte Count Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-12 RES Reserved locations. Read and written as zeros. 11-0 NRBC Next Receive Byte Count. This field is a copy of the BCNT field of RMD1 of the next receive de- scriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR45: Next Receive Status Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NRST Next Receive Status. This field is a copy of bits 31-16 of RMD1 of the next receive descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR46: Transmit Poll Time Counter Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 TXPOLL Transmit Poll Time Counter. This counter is incremented by the Am79C971 controller microcode and is used to trigger the transmit descriptor ring polling operation of the Am79C971 controller. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR47: Transmit Polling Interval Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 TXPOLLINT Transmit Polling Interval. This register contains the time that the Am79C971 controller will wait be- tween successive polling opera- tions. The TXPOLLINT value is expressed as the two’s comple- ment of the desired interval, where each bit of TXPOLLINT represents 1 clock period of time. TXPOLLINT[3:0] are ignored. (TXPOLLINT[16] is implied to be a one, so TXPOLLINT[15] is sig- nificant and does not represent the sign of the two’s complement TXPOLLINT value.) |
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