AM79C971VCW datasheet(140/265 Pages) AMD

140 / 265 page

140

Am79C971

P R E L I M INARY

dress pins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE32 bit has no effect on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0

SWSTYLE

Software Style register. The val-

ue in this register determines the

style of register and memory re-

sources that shall be used by the

Am79C971 controller. The Soft-

ware Style selection will affect the

interpretation of a few bits within

the CSR space, the order of the

descriptor entries and the width of

the descriptors and initialization

block entries.

All Am79C971 controller CSR

bits and BCR bits and all descrip-

tor, buffer, and initialization block

entries not cited in Table 26 are

unaffected by the Software Style

selection and are, therefore, al-

ways fully functional as specified

in the CSR and BCR sections.

Read/Write accessible only when

either the STOP or the SPND bit

is set. The SWSTYLE register will

contain the value 00h following

H_RESET and will be unaffected

by S_RESET or STOP.

CSR60: Previous Transmit Descriptor Address

Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

PXDAL

Contains the lower 16 bits of the

previous transmit descriptor ad-

dress pointer. Am79C971 con-

troller has the capability to stack

multiple transmit frames.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR61: Previous Transmit Descriptor Address

Upper

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

PXDAU

Contains the upper 16 bits of the

transmit

descriptor

address pointer. The Am79C971

controller has the capability to

stack multiple transmit frames.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

Table 26.

Software Styles

SWSTYLE

[7:0]

Style

Name

SSIZE32

Initialization Block

Entries

Descriptor Ring Entries

00h

LANCE/

PCnet-ISA

controller

16-bit software structures,

non-burst or burst access

16-bit software structures,

non-burst access only

01h

RES

02h

PCnet-PCI

controller

32-bit software structures,

non-burst or burst access

32-bit software structures,

non-burst access only

03h

PCnet-PCI

controller

32-bit software structures,

non-burst or burst access

32-bit software structures,

non-burst access only

All Other

Reserved

Undefined

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