AM79C971VCW datasheet(144/265 Pages) AMD

144 / 265 page

144

Am79C971

P R E L I M INARY

When an external SRAM is used,

SRAM_SIZE > 0, there is a re-

striction that the number of bytes

written is a combination of bytes

written into the Bus Transmit

FIFO and the MAC Transmit

FIFO. The Am79C971 controller

supports a mode that will wait un-

til a full packet is available before

commencing with the transmis-

sion of preamble. This mode is

useful in a system where high la-

tencies cannot be avoided. See

Table 28.

Transmit Start Point Programming

NOTE: A “No SRAM configuration” is

only valid for 10Mb mode. In 100Mb

mode, SRAM is mandatory and must

always be used.

Read/Write accessible only when

either the STOP or the SPND bit

is set. XMTSP is set to a value of

01b (64 bytes) after H_RESET or

S_RESET and is unaffected by

STOP.

9-8

XMTFW[1:0] Transmit FIFO Watermark. XMT-

FW specifies the point at which

transmit

DMA

requested,

based upon the number of bytes

that could be written to the Trans-

mit FIFO without FIFO overflow.

Transmit DMA is requested at

any time when the number of

bytes specified by XMTFW could

be written to the FIFO without

causing Transmit FIFO overflow,

and the internal microcode en-

gine has reached a point where

the Transmit FIFO is checked to

determine if DMA servicing is re-

quired.

When operating in the NO-SRAM

mode

(no

SRAM

present),

SRAM_SIZE set to 0, the Bus

Transmit FIFO and the MAC

Transmit FIFO operate like a sin-

gle FIFO and the watermark val-

ue selected by XMTFW[1:0] sets

the number of FIFO byte loca-

tions that must be available in the

FIFO before receive DMA is re-

quested.

NOTE: A “No SRAM configura-

tion” is only valid for 10Mb mode.

In 100Mb mode, SRAM is man-

datory and must always be used.

When operating with an external

SRAM, the Bus Transmit FIFO

and the MAC Transmit FIFO op-

erate independently on the bus

side and MAC side of the external

SRAM, respectively. In this case,

the watermark value set by XMT-

FW[1:0] sets the number of FIFO

byte locations that must be avail-

able in the Bus Transmit FIFO.

See Table 29.

Read/Write accessible only when

either the STOP or the SPND bit

is set. XMTFW is set to a value of

00b (16 bytes) after H_RESET or

S_RESET and is unaffected by

STOP.

7-0

DMATC[7:0] DMA Transfer Counter. Writing

and reading to this field has no ef-

fect.

Use

MAX_LAT

and

MIN_GNT in the PCI configura-

tion space.

CSR82: Transmit Descriptor Address Pointer Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

XMTSP[1:0]

SRAM_SIZE

Bytes Written

128

248

128

Full Packet

Table 29.

Transmit Watermark Programming

XMTFW[1:0]

Bytes Available

108

Reserved

AM79C971VCW 数据表(PDF) 144 Page - Advanced Micro Devices

AM79C971VCW 数据表(HTML) 144 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载