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AM79C971VCW 数据表(PDF) 142 Page - Advanced Micro Devices |
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AM79C971VCW 数据表(HTML) 142 Page - Advanced Micro Devices |
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142 / 265 page  142 Am79C971 P R E L I M INARY CSR72: Receive Ring Counter Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 RCVRC Receive Ring Counter location. Contains a two’s complement bi- nary number used to number the current receive descriptor. This counter interprets the value in CSR76 as pointing to the first de- scriptor. A counter value of zero corresponds to the last descriptor in the ring. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR74: Transmit Ring Counter Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 XMTRC Transmit Ring Counter location. Contains a two’s complement bi- nary number used to number the current transmit descriptor. This counter interprets the value in CSR78 as pointing to the first de- scriptor. A counter value of zero corresponds to the last descriptor in the ring. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR76: Receive Ring Length Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 RCVRL Receive Ring Length. Contains the two’s complement of the re- ceive descriptor ring length. This register is initialized during the Am79C971 controller initializa- tion routine based on the value in the RLEN field of the initialization block. However, this register can be manually altered. The actual receive ring length is defined by the current value in this register. The ring length can be defined as any value from 1 to 65535. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR78: Transmit Ring Length Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 XMTRL Transmit Ring Length. Contains the two’s complement of the transmit descriptor ring length. This register is initialized during the Am79C971 controller initial- ization routine based on the value in the TLEN field of the initializa- tion block. However, this register can be manually altered. The ac- tual transmit ring length is defined by the current value in this regis- ter. The ring length can be de- fined as any value from 1 to 65535. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR80: DMA Transfer Counter and FIFO Threshold Control Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-14 RES Reserved locations. Written as zeros and read as undefined. 13-12 RCVFW[1:0] Receive FIFO Watermark. RCVFW controls the point at which receive DMA is requested in relation to the number of re- ceived bytes in the Receive FIFO. RCVFW specifies the number of bytes which must be present (once the frame has been verified as a non-runt) before receive |
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