AM79C971VCW datasheet(143/265 Pages) AMD

143 / 265 page

Am79C971

143

P R E L I M INARY

DMA is requested. Note however

that, if the network interface is op-

erating in half-duplex mode, in or-

der

for

receive

DMA

performed for a new frame, at

least 64 bytes must have been re-

ceived. This effectively avoids

having to react to receive frames

which are runts or suffer a colli-

sion during the slot time (512 bit

times). If the Runt Packet Accept

feature is enabled or if the net-

work interface is operating in full-

duplex mode, receive DMA will

be requested as soon as either

the RCVFW threshold is reached,

or a complete valid receive frame

is detected (regardless of length).

When the FDRPAD (BCR9, bit 2)

is set and the Am79C971 control-

ler is in full-duplex mode, in order

to receive DMA to be performed

for a new frame, at least 64 bytes

must have been received. This

effectively disables the runt pack-

et accept feature in full duplex.

When operating in the NO-SRAM

mode (no SRAM present), the

Bus Receive FIFO and the MAC

Receive operate like a single

FIFO and the watermark value

selected by RCVFW[1:0] sets the

number of bytes that must be

present in the FIFO before re-

ceive DMA is requested.

NOTE: A “No SRAM configura-

tion” is only valid for 10Mb mode.

In 100Mb mode, SRAM is man-

datory and must always be used.

When operating with an external

SRAM, the Bus Receive FIFO,

and the MAC Receive FIFO oper-

ate independently on the bus side

and MAC side of the external

SRAM, respectively. In this case,

the

watermark

value

set

RCVFW[1:0] sets the number of

bytes that must be present in the

Bus Receive FIFO only. See Ta-

ble 27.

Table 27.

Receive Watermark Programming

Read/Write accessible only when

either the STOP or the SPND bit

is set. RCVFW[1:0] is set to a val-

01b

(64

bytes)

after

H_RESET or S_RESET and is

unaffected by STOP.

11-10 XMTSP[1:0] Transmit Start Point. XMTSP

controls the point at which pream-

ble transmission attempts to com-

mence in relation to the number

of bytes written to the MAC

Transmit FIFO for the current

transmit frame. When the entire

frame is in the MAC Transmit

FIFO, transmission will start re-

gardless of the value in XMTSP.

If the network interface is operat-

ing in half-duplex mode, regard-

less of XMTSP, the FIFO will not

internally overwrite its data until

at least 64 bytes (or the entire

frame if shorter than 64 bytes)

have been transmitted onto the

network. This ensures that for

collisions within the slot time win-

dow, transmit data need not be

rewritten to the Transmit FIFO,

and retries will be handled auton-

omously by the MAC. If the Dis-

able Retry feature is enabled, or if

the network is operating in full-du-

plex mode, the Am79C971 con-

troller

can

overwrite

the

beginning of the frame as soon as

the data is transmitted, because

no collision handling is required in

these modes.

Note

that

when

external

SRAM is being used, if the NOU-

FLO bit (BCR18, bit 11) is set to

1, there is the additional restric-

tion that the complete transmit

frame must be DMA’d into the

Am79C971 controller and reside

within a combination of the Bus

Transmit

FIFO,

the

external

SRAM, and the MAC Transmit

FIFO.

RCVFW[1:0]

Bytes Received

112

Reserved

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